DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 7-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7-8 each recite “contacts” and depend ultimately on claim 1 which already introduces “contacts”. The manner in which the claim introduces “contacts” twice separately despite them appearing to be separate elements does not particularly point out and distinctly claim the Applicant’s invention.
For the purposes of compact prosecution the interpretation will be taken the newly introduced contacts in claims 7-8 are additional contacts.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim 1 is rejected under 35 U.S.C. 102(a1)&(a2) as being anticipated by Sakamoto et al. (US 2016/0071850 A1), hereinafter as S1
5. Regarding Claim 1, S1 discloses a method for manufacturing an integrated circuit (see Figs. 2-10), comprising:
forming a conductive layer (element M1, see [0041] “interconnection M1”) above a front face (top face) of a semiconductor substrate (element SB, see [0035] “semiconductor substrate SB”);
forming a pre-metal dielectric region (element INS3, see [0044] “interlayer dielectric INS3”) above the conductive layer (see Fig. 7);
forming a trench (element CGV, see [0044] “trenches CGV”) within the pre-metal dielectric region (see Fig. 7);
forming at least one metal-insulator-metal-type capacitive structure (see Fig. 9 element CON, see [0047] “capacitive elements CON”) in said trench by:
forming a first metal layer (see Fig. 8 element EL, see [0045] “lower electrodes EL, a metal or metal-element-containing material is usable”) configured to be electrically connected with the conductive layer (see Fig. 8), forming a dielectric layer (see Fig. 9 element CINS, see [0045] “capacitive insulator film CINS”) on the first metal layer, and forming a second metal layer (element EU, see [0048] “upper electrode has a structure of three metal films”) on the dielectric layer (see Fig. 9);
forming contacts extending through the pre-metal dielectric region (see Figs. 1, 10 elements PLG3 for the plurality of cells); and
forming an interconnection part (elements M2, see [0054] “interconnection M2 may be a copper interconnection, and is formed to have a laminated structure of the following two: a thin bather conductor film (such as a tantalum (Ta) film, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a laminated film of two or more of these films) functioning as a barrier metal; and a main conductor film (such as a copper (Cu) film) that is larger in film thickness than the barrier conductor film”) of the integrated circuit including a stack of metal levels (see [0054]) on an upper surface of the pre-metal dielectric region (see Fig. 2);
wherein said stack of metal levels includes a metal track (track of element M2) for a metal level of said stack which is closest to the pre-metal dielectric region (see Fig. 2 element M2 of the stack has a bottom metal layer which is closest to element INS3); and
wherein the contacts electrically connect the second metal layer of said at least one metal-insulator-metal-type capacitive structure with said metal track (see Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 2 is rejected under 35 U.S.C. 103 as obvious over Sakamoto et al. (US 2016/0071850 A1), hereinafter as Sakamoto in view of Sinha (US 2003/0203633 A1), hereinafter as S2, in view of Sandhu et al. (US 2002/0195642 A1), hereinafter as S3
7. Regarding Claim 2, S1 discloses the method according to claim 1,
the method further comprising:
performing a non-oxidizing annealing (see [0073] “After the formation of the lower electrode EL, the workpiece is annealed to crystalize the titanium nitride film.” And [0075] “After the formation of the capacitive insulator film CINS, the workpiece is annealed … This annealing makes it possible to improve the capacitive insulator film CINS in film quality and dielectric constant.” The annealing is performed in an atmosphere without oxygen)
S1 does not disclose wherein the conductive layer is formed of polycrystalline silicon, wherein forming the conductive layer comprises a silicidation forming a thin layer of metal silicide on the polycrystalline silicon of the conductive layer, and wherein forming the first metal layer comprises forming a diffusion barrier layer, the method further comprising:
Annealing to generate a chemical bond between the diffusion barrier layer and the thin layer of metal silicide.
S2 discloses (see Fig. 11) wherein the conductive layer (element 60, 55, see [0051] “conductive plug 60 encompasses a doped polysilicon material … contact enhancement material layer 55 encompassing a metal silicide (such as titanium silicide)”) is formed of polycrystalline silicon (element 60 see [0051]), wherein forming the conductive layer comprises a silicidation (element 55 see [0051]) forming a thin layer of metal silicide on the polycrystalline silicon of the conductive layer (see Fig. 11 [0052, 0030-0031] metal nitride diffusion barrier contacting the metal silicide), and wherein forming the first metal layer comprises forming a diffusion barrier layer (element 36c, see [0052] “Material layer 36c, however, encompasses a diffusion barrier material”).
The material of the conductive layer and silicidation, and the diffusion barrier layer first metal layer as taught by S2 is incorporated as material of the conductive layer and silicidation, and the diffusion barrier layer first metal layer of S1.
S1, S2 do not explicitly disclose the annealing is to generate a chemical bond between the diffusion barrier layer and the thin layer of metal silicide.
S1 discloses forming a silicide by annealing to generate a chemical bond between the diffusion barrier layer and the thin layer of metal silicide (see [0043] “The titanium nitride layer 75 provides a barrier against silicon diffusion of the polysilicon plug 65 and the titanium silicide layer 67 during subsequent high temperature anneals”; note, the silicidation at the interface of the two materials indicates a chemical bond to a certain degree)
The annealing to form the metal silicide with a resulting chemical bond as taught by S1 is incorporated as annealing to form the metal silicide with a resulting chemical bond of S1, S2.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S3 with S1,S2 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming a silicide for another to obtain predictable results (see S3 [0043]).
8. Claim 3 is rejected under 35 U.S.C. 103 as obvious over Sakamoto et al. (US 2016/0071850 A1), hereinafter as Sakamoto in view of Sinha (US 2003/0203633 A1), hereinafter as S2, in view of Pai et al. (US 2013/0292794 A1), hereinafter as P1
9. Regarding Claim 3, S1 discloses the method according to claim 1, wherein forming said trench comprises etching a trench (see Fig. 7 element CGV, and [0071] “subject the interlayer dielectric INS3 to dry etching, thereby making the capacitor-forming trenches CGV”) opening in the pre-metal dielectric region (see Fig. 7), and wherein forming the first metal layer comprises performing a conformal deposition conforming to the sides and the bottom of the trench opening (see Fig. 8 and [0072] “The titanium nitride (TiN) film can be formed into a desired thickness, for example, by repeating, plural times, a cycle of depositing tetrakisdimethylaminotitanium (TDMAT) into the capacitor-forming trench CGV”), wherein forming the dielectric layer comprises performing a conformal deposition conforming to a surface of the first metal layer (see [0074] “by an ALD method”), and wherein forming the second metal layer comprises performing an excess deposition conforming to the dielectric layer and filling said trench opening (see Fig. 9).
S1 does not disclose the method further comprising performing a mechanical-chemical planarization to remove excess portions of the second metal layer located outside the trench opening.
P1 discloses (see Figs. 4-7 and [0024] “Subsequently, the portions of the metal layer outside the trenches 180 and 182 are removed by a suitable process such as chemical mechanical polishing (CMP)”)
The capacitor planarization as taught by P1 is incorporated as a capacitor planarization of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of P1 with S1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known trench upper surface relationship with an embedded capacitor for another to obtain predictable results (see P1 [0024]).
10. Claim 4 is rejected under 35 U.S.C. 103 as obvious over Sakamoto et al. (US 2016/0071850 A1), hereinafter as Sakamoto in view of Sinha (US 2003/0203633 A1), hereinafter as S2, in view of Lee et al. (US 2009/0244971 A1), hereinafter as L1
11. Regarding Claim 4, S1 discloses the method according to claim 1.
S1 does not explicitly disclose wherein forming the conductive layer comprises forming a dielectric interface electrically insulating the conductive layer from the semiconductor substrate, wherein the conductive layer and the dielectric interface form, with the semiconductor substrate, a capacitive structure of a metal-oxide-semiconductor type.
L1 discloses (see Figs. 6-7) a dielectric interface (dielectric element of the MOS capacitor element 250, see [0045] “MOS capacitor 250”) that electrically insulates between the conductive layer and the semiconductor substrate (the conductive layer of element 250 connecting to the bottom MIM metal level of element 260, see [0045]), wherein the conductive layer and the dielectric interface are configured to form, with the semiconductor substrate, a capacitive structure of a metal-oxide-semiconductor type (see Figs. 6-7 and [0045]).
The MOS capacitor interface between the MIM capacitor in an upper layer and substrate as taught by L1 is incorporated as a MOS capacitor interface between the MIM capacitor in an upper layer and substrate of S1 (see S1 Fig. 2 the element CON is configured to connect to a gate of a MOS capacitor), wherein the combination discloses further comprising a dielectric interface that electrically insulates between the conductive layer and the semiconductor substrate, wherein the conductive layer and the dielectric interface are configured to form, with the semiconductor substrate, a capacitive structure of a metal-oxide-semiconductor type.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with S1 because the combination provides coupling MOS capacitors stacked with MIM capacitors providing area efficient coupling, and leakage current balancing in a memory device (see L1 [0024-0028, 0044-0046]), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known MIM memory capacitor electrical connection interface with the semiconductor substrate for another in a similar device to obtain predictable results (see L1 Fig. 7 and [0024-0028, 0044-0046]).
12. Claim 5 is rejected under 35 U.S.C. 103 as obvious over Sakamoto et al. (US 2016/0071850 A1), hereinafter as Sakamoto in view of Sinha (US 2003/0203633 A1), hereinafter as S2, in view of Xu et al. (US 2018/0122795 A1), hereinafter as X1
13. Regarding Claim 5, S1, L1 discloses the method according to claim 4.
S1, L1 do not explicitly disclose wherein forming the conductive layer comprises: etching at least one trench extending in depth into the semiconductor substrate perpendicularly to a surface of the semiconductor substrate; filling said at least one trench with a conductive material overflowing from the at least one trench above a part of said surface, wherein the conductive layer includes a horizontal part covering said surface and at least one vertical part extending deep into the semiconductor substrate perpendicularly to said surface.
X1 discloses wherein forming the conductive layer comprises: etching at least one trench extending in depth into the semiconductor substrate perpendicularly to a surface of the semiconductor substrate (see [0022] “Trench 138 may be formed using any now known or later developed photolithography techniques prior to formation of gate stack 150 (FIG. 5), e.g., patterning a photoresist, and etching to form a mask and etching to form trench 138.”)
The etching to form the trench as taught by X1 is incorporated as etching to form the trench of S1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of X1 with S1, L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming a trench for a trench capacitor for another in a similar device to obtain predictable results (see X1 [0022]).
S1, L1, X1 do not explicitly disclose filling said at least one trench with a conductive material overflowing from the at least one trench above a part of said surface, wherein the conductive layer includes a horizontal part covering said surface and at least one vertical part extending deep into the semiconductor substrate perpendicularly to said surface.
S3 discloses (see Fig. 5) filling said at least one trench with a conductive material (element 68, see Column 6 lines 40-41 “conductive material 68 (e.g., metal, doped polysilicon, etc.)”) overflowing from the at least one trench above a part of said surface (see Fig. 5), wherein the conductive layer includes a horizontal part (upper lateral horizontal part) covering said surface and at least one vertical part (center vertical part) extending deep into the semiconductor substrate perpendicularly to said surface (see Fig. 5)
The shape of the trench capacitor as taught by S2 is incorporated as the shape of the trench capacitor of S1, L1, X1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with S1, L1, X1 because the combination allows a trench capacitive storage in a read circuitry of a memory (see S3 Column 5 lines 25-29), wherein the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known capacitor type for another to obtain predictable results, wherein the two are provided as alternatives (see S3 Figs. 4-5 and Column 6 lines 6-9 and 30-31).
14. Claim 9 is rejected under 35 U.S.C. 103 as obvious over Sakamoto et al. (US 2016/0071850 A1), hereinafter as Sakamoto in view of Sinha (US 2003/0203633 A1), hereinafter as S2, in view of Rahim et al. (US 2010/0148304 A1), hereinafter as R1
15. Regarding Claim 9, S1 discloses the method according to claim 1.
S1 does not explicitly disclose further comprising: forming a resistive conductive bar of a resistive element having two terminals, wherein the conductive layer is formed above the resistive conductive bar; and electrically connecting the metal track of the metal level of said stack which is closest to the pre-metal dielectric region, the conductive layer, and the terminals of the resistive element so as to form a resistive-capacitive circuit with said at least one capacitive structure of the metal-insulator-metal type.
R1 discloses (see Figs. 1-13, in particular see Fig. 13) further comprising: forming a resistive conductive bar (see Figs. 12-13 element 70, see [0071] “resistor 70”) of a resistive element having two terminals (a left terminal connected to element 65 and a right terminal connected to element 51), wherein the conductive layer is formed above the resistive conductive bar (conductive layer of element 60,65 located above element 70); and electrically connecting the metal track (see Fig. 1 element 46 of element 38, see [0074] “power lines 46” and [0033] “each component 38 may represent a block of programmable logic, a memory block”) of the metal level of said stack which is closest to the pre-metal dielectric region, the conductive layer, and the terminals of the resistive element so as to form a resistive-capacitive circuit (see Figs. 12-13), with said at least one capacitive structure of the metal-insulator-metal type (see [0056] “Capacitors 60 for the capacitor cells 50 may be implemented as metal-insulator-metal (MIM)”)
The resistive bar of the resistive-capacitive circuit connecting to the memory as taught by R1 is incorporated as a resistive bar of the resistive-capacitive circuit connecting to the memory of S1 (see S1 Fig. 1 a resistive-capacitive circuit is incorporated connected to the memory capacitor element CON and see Fig. 2 incorporated between element CON and substrate element SB).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of R1 with S1 because the combination allows for noise reduction with increased effectiveness located proximate to circuit components and conserve integrated circuit real estate (see R1 [0028, 0034-0037, 0075]), wherein the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known coupling structure with the substrate to a memory for another to obtain predictable results (see Rahim Figs. 1, 12-13, and [0033] “each component 38 may represent a block of programmable logic, a memory block”).
Allowable Subject Matter
16. Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
17. Claim 6, “etching said at least one trench and filling said at least one trench are carried out simultaneously with etching and filling to form a buried access transistor with a vertical gate for memory cells of a non-volatile memory” – as instantly claimed and in combination with the additionally claimed limitations.
18. Claim 7, “further comprising forming contacts to electrically connect the conductive layer with a further metal track of the metal level of said stack which is closest to the pre-metal dielectric region, and forming contacts to electrically connect the semiconductor substrate with another metal track of the metal level of said stack which is closest to the pre-metal dielectric region, wherein the further metal track and the another metal track are electrically connected with each other” – as instantly claimed and in combination with the additionally claimed limitations.
19. Claim 8, “further comprising forming contacts to electrically connect the conductive layer with a further metal track of the metal level of said stack which is closest to the pre-metal dielectric region, and forming contacts to electrically connect the semiconductor substrate with another metal track of the metal level of said stack which is closest to the pre-metal dielectric region, wherein the further metal track and the another metal track are electrically connected with the metal track” – as instantly claimed and in combination with the additionally claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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