DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/11/2024, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6 is/are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Park et al. (US 20240332150) herein referred to as Park, Hwanjoo. (Fig. 1)
As to claim 1, a semiconductor package comprising:
a first redistribution layer ([0046] Fig. 1, 1st redistribution wirings 100/102); a first semiconductor device ([0052] Fig. 1, 1st lower semiconductor chip 200a) disposed on the first redistribution layer (Fig. 1, 100/102);
a second semiconductor device ([0052] Fig. 1, 2nd lower semiconductor chip 200b) disposed on the first redistribution layer (Fig. 1, 100/102) and adjacent to the first semiconductor device (200a);
a support member ([0050] Fig. 1, support layer between (402) and 101b) disposed at side surfaces of the first semiconductor device (Fig. 1, 200a) and the second semiconductor device (Fig. 1, 200b);
a third semiconductor ([0057] Fig. 1, upper semiconductor chip 600) device disposed above the second semiconductor device (Fig. 1, 200b); and
a heat dissipation structure (first heat dissipation block 700a and the second heat dissipation block 700b) disposed above the first semiconductor device (Fig. 1, 200a) and adjacent to the third semiconductor device (Fig. 1, 600).
As to claim 5, the semiconductor package of claim 1, wherein
the third semiconductor device (Fig. 1, 600) overlaps at least a part of the first semiconductor device (Fig. 1, 200a) in a vertical direction.
As to claim 6, the semiconductor package of claim 1, further comprising
a second redistribution layer ([0046] Fig. 1, 2nd redistribution wirings 500/502); disposed on the first semiconductor device (Fig. 1, 200a)
the second semiconductor device (Fig. 1, 200b), and the support member (Fig. 1, support layer between (402) and 101b), wherein
the third semiconductor device (Fig. 1, 600) and the heat dissipation structure (Fig. 1, 700a/700b) are disposed on the second redistribution layer (Fig. 1, 500/502).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, Hwanjoo et al. (US 20240332150) in view of Lee et al. (US 20190043847)
As to claim 10, Park discloses the semiconductor package of claim 1, wherein
the third semiconductor device (Fig. 1, 600); comprises a memory package including at least one memory chip ([0052] Fig. 1, upper semiconductor chip 600 may include a memory chip).
Park, Hwanjoo does not appear to expressly disclose "the second semiconductor device (Fig. 1, 200b) comprises a power management IC (PMIC) package”. A Power Management IC (PMIC) converts, regulates, sequences, and monitors various voltages, ensuring complex components receive the precise power required while protecting against thermal and electrical faults.
Lee includes a power management integrated circuit (PMIC) taught in [0007], on one of its three semiconductor packages. It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to modify Park such that a PMIC is included in the design as is taught by Lee, so as to optimize power consumption.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, Hwanjoo et al. (US 20240332150) in view of Chen et al. (US 20080157344) Fig. 3B
As to claim 11, Park teaches the semiconductor package of claim 1, as discussed above but does not appear to expressly disclose “a passive element disposed on a bottom surface of the first redistribution layer.”
Chen et al. teaches a passive element disposed on a bottom surface of the first redistribution layer in [0034]. “In some example embodiments, at least one passive element 181 may be attached to the bottom surface of the first package substrate 101.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to modify Park such that a passive element disposed on a bottom surface of the first redistribution layer, as is taught by Chen because using a passive element (like a resistor, capacitor, or inductor) in an RDL (Redistribution Layer) improves electrical performance.
Allowable Subject Matter
Claims 12 and 17 are allowed. The following is an examiner's statement of reasons for allowance: The prior art taken either singularly or in combination, fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art, Park et al. (US 20240332150) herein referred to as Park, Hwanjoo, fails to teach a combination of all of the features in the claims.
As to claim 12, a semiconductor package comprising:
a first redistribution layer ([0046] Fig. 1, 1st redistribution wirings 100/102);
a first semiconductor device ([0052] Fig. 1, 1st lower semiconductor chip 200a) disposed on the first redistribution layer (Fig. 1, 100/102);
a second semiconductor device ([0052] Fig. 1, 2nd lower semiconductor chip 200b) disposed on the first redistribution layer (Fig. 1, 100/102) and adjacent to the first semiconductor device (Fig. 1, 200a)
a support member ([0050] Fig. 1, support layer between (402) and 101b) disposed at side surfaces of the first semiconductor device (Fig. 1, 200a) and the second semiconductor device (Fig. 1, 200b)
a second redistribution layer ([0046] Fig. 1, 2nd redistribution wirings 500/502); disposed on the first semiconductor device (Fig. 1, 200a), the second semiconductor device (Fig. 1, 200b), and the support member ([0050] Fig. 1, support layer between (402) and 101b);
a third semiconductor device ([0057] Fig. 1, upper semiconductor chip 600) disposed on the second redistribution layer (Fig. 1 500/502) above the second semiconductor device (Fig. 1, 200b); and
a heat dissipation structure ([0057] Fig. 1, upper semiconductor chip 600) disposed on the second redistribution layer (Fig. 1 500/502) above at least a part of the first semiconductor device (Fig. 1, 200a) and adjacent to the third semiconductor device (Fig. 1, 600), wherein
the support member Fig. 1, support layer between (402) and 101b);
comprises a through-hole region (exposed areas of (100/102) near conductive vias (300), 200a and 200b) exposing the first redistribution layer, and
Park, Hwanjoo does not teach:
a groove region including a depression in the support member, and wherein
the first semiconductor device (Fig. 1, 200a) is disposed in the through-hole region and the second semiconductor device (Fig. 1, 200b) is disposed in the groove region.
As to claim 17, Park, Hwanjoo teaches a semiconductor package comprising:
a first redistribution layer ([0046] Fig. 1, 1st redistribution wirings 100/102); a first semiconductor device ([0052] Fig. 1, 1st lower semiconductor chip 200a) disposed on the first redistribution layer;
a second semiconductor device ([0052] Fig. 1, 2nd lower semiconductor chip 200b) disposed on the first redistribution layer and adjacent to the first semiconductor device;
a support member ([0050] Fig. 1, support layer between (402) and 101b) including a through-hole region (See Fig. 1) in which the first semiconductor device is disposed and
a third semiconductor device ([0057] Fig. 1, upper semiconductor chip 600) disposed above the second semiconductor device; and
a heat dissipation structure (first heat dissipation block 700a and the second heat dissipation block 700b) disposed above at least a part of the first semiconductor device and adjacent to the third semiconductor device, wherein
the through-hole region exposes the first redistribution layer, and wherein
Park, Hwanjoo does not teach:
a groove region in which the second semiconductor device is disposed;
the groove region including a depression in the support member and having a width that increases as a distance from the support member increases.
Claim(s) 2, 7 and 8 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 2, Park, Hwanjoo teaches the semiconductor package of claim 1, wherein
the support member ([0050] Fig. 1, support layer between (402) and 101b) comprises a through-hole region (exposed areas of (100/102) near conductive vias (300), 200a and 200b) exposing the first redistribution layer (Fig. 1, 100/102), and
Park, Hwanjoo does not teach:
a groove region including a depression in the support member (Fig. 1, 400) wherein the first semiconductor device is disposed in the through-hole region (exposed areas of (100/102) near conductive vias (300), 200a and 200b) and
the second semiconductor device (Fig. 1, 200b) is disposed in the groove region, and wherein
the support member ([0050] Fig. 1, support layer between (402) and 101b) surrounds the side surfaces of the first semiconductor device (Fig. 1, 200a) and the second semiconductor device (Fig. 1, 200b).
As to claim 7, Park, Hwanjoo teaches the semiconductor package of claim 6, further comprising
a sealant ([0050] Fig. 1 sealing member 400) disposed on a bottom surface of the second redistribution layer (Fig. 1, 500/502), wherein the sealant covers side surfaces and top surfaces of the first semiconductor device (Fig. 1, 200a) and side surfaces and top surfaces of the second semiconductor device (Fig. 1, 200b), and wherein
Park, Hwanjoo does not teach:
the second semiconductor device (Fig. 1, 200b) is connected to the third semiconductor device (Fig. 1, 600) through second connection terminals disposed on a top surface of the second semiconductor device (Fig. 1, 200b) and through electrodes connected to the second connection terminals and penetrating the sealant (Fig. 1, 400).
As to claim 8, Park, Hwanjoo teaches the semiconductor package of claim 1.
Park, Hwanjoo does not teach:
the first semiconductor device (Fig. 1, 200a) comprises a first semiconductor chip and a second semiconductor chip, wherein
the first semiconductor chip (Fig. 1, 200a) is mounted on the first redistribution layer ([0046] Fig. 1, 1st redistribution wirings 100/102) through first connection terminals disposed on a bottom surface of the first semiconductor chip, and wherein the second semiconductor chip is disposed on a top surface of the first semiconductor chip.
Claims 3 -4 , 9, 13-16 and 18-20 are allowable at least because they depend from allowable claim 2, allowable claim 8 and allowed independent claims 12 and 17, respectively.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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