Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 12 is objected to because of the following informalities:
Informality #1 is a repeating word seen underlined in limitation “and the and the electrically conductive fused region electrically connects the frontside metal line to...”.
Informality #2 is an acronym with a missing description seen in limitation “between a frontside (BEOL) structure including a frontside metal line and a…”. Separate claims trees require a description for the acronyms.
Appropriate correction is required. Claim 12 will be examined with the fixed informalities below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6, 11-12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kannan et al. (US-20160225679-A1 referred as Kannan) in view of Shen et al. (US-20220285434-A1 referred as Shen).
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Figure 8 annotated
Regarding claim 1. Kannan discloses a semiconductor device comprising: a d-fuse structure comprising a plurality of d-fuse vias located between a frontside back-end-of-the-line (BEOL) structure comprising a frontside metal line and a backside power distribution network comprising a backside power distribution network metal line ([0044], figure 8 annotated above, a plurality of d-fuse vias #f1 is located between a frontside metal line #fml and a backside power distribution network metal line #803. Please note the frontside metal line #fml contains conductive metal since [0045] states there is continuity from conductive elements #803 to #845. Additionally, please note the backside power distribution network metal line #803 is made to advert power/ground therefore able to function as power distribution), and the d-fuse vias are connected to the frontside metal line and the backside power distribution network metal line in a staggered pattern ([0044], figure 8 annotated above, the plurality of d-fuse vias #f1 and the frontside metal line #fml and the backside power distribution network metal line #803 are connected in a staggered pattern).
Kannan lacks wherein the d-fuse vias have a first portion embedded in a shallow trench isolation structure and a second portion embedded in a middle-of-the-line (MOL) dielectric layer.
Shen discloses wherein the d-fuse vias have a first portion embedded in a shallow trench isolation structure and a second portion embedded in a middle-of-the-line (MOL) dielectric layer ([0036], figure 3B with a detailed view in figure 2D, the d-fuse vias #TV have a first portion embedded in a shallow trench isolation structure #222-1 and a second portion embedded in a MOL dielectric layer #222-0).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kannan to include wherein the d-fuse vias have portions in the shallow trench isolation structure and the middle-of-the-line (MOL) dielectric layer as taught by Shen in order to enhance electrical isolation, reduce device failures, and to extend the devices lifetime.
Regarding claim 4. Kannan as modified discloses wherein each d-fuse via of the plurality of d-fuse vias is composed of an electrically conductive metal or electrically conductive metal alloy ([0044], figure 8, each d-fuse via #f1 is made of electrically conductive metal since are made of vias #821/823/825/827 and metal layers #829/831/833)
Regarding claim 6. Kannan as modified lacks wherein each d-fuse via of the plurality of d-fuse vias is spaced apart and separated from each other by both the MOL dielectric layer and the shallow trench isolation structure.
Shen discloses wherein each d-fuse via of the plurality of d-fuse vias is spaced apart and separated from each other by both the MOL dielectric layer and the shallow trench isolation structure ([0036], figure 3B with a detailed view in figure 2D, each d-fuse vias #TV are spaced apart and separated by both the shallow trench isolation structure #222-1 and the MOL dielectric layer #222-0).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kannan as modified to include wherein the d-fuse vias are spaced apart from each other with the shallow trench isolation structure and the middle-of-the-line (MOL) dielectric layer in between them as taught by Shen in order to enhance electrical isolation, reduce device failures, and to extend the devices lifetime.
Regarding claim 11. Kannan as modified discloses at least one transistor located adjacent to the d-fuse structure, wherein the at least one transistor is electrically connected to another frontside metal line of the BEOL structure ([0038, 0044], figure 5 and figure 8 annotated above, at least one transistor #807 is located adjacent to the d-fuse structure #803/f1/fml, and the transistor #807 is electrically connected to another frontside metal line #819 (the metal layer #819 is part of the frontside metal line #fml)).
Regarding claim 12. Kannan discloses a semiconductor device comprising: a d-fuse structure comprising an electrically conductive fused region located between a frontside back-end-of-the-line (BEOL) structure including a frontside metal line and a backside power distribution network including a backside power distribution network metal line ([0044], figure 8 annotated above, a electrically conductive fused region #f1 is located between a frontside metal line #fml and a backside power distribution network metal line #803. Please note the frontside metal line #fml contains conductive metal since [0045] states there is continuity from conductive elements #803 to #845. Additionally, please note the backside power distribution network metal line #803 is made to advert power/ground therefore able to function as power distribution), and the electrically conductive fused region electrically connects the frontside metal line to the backside power distribution network metal line ([0044], figure 8 annotated above, the electrically conductive fused region #f1 electrically connects the frontside metal line #fml and the backside power distribution network metal line #803).
Kannan lacks wherein the electrically conductive fused region has a first portion embedded in a shallow trench isolation structure and a second portion embedded in a middle-of-the-line (MOL) dielectric layer.
Shen discloses wherein the electrically conductive fused region has a first portion embedded in a shallow trench isolation structure and a second portion embedded in a middle-of-the-line (MOL) dielectric layer ([0036], figure 3B with a detailed view in figure 2D, the electrically conductive fused region #TV has a first portion embedded in a shallow trench isolation structure #222-1 and a second portion embedded in a MOL dielectric layer #222-0).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kannan to include wherein the electrically conductive fused region have portions in the shallow trench isolation structure and the middle-of-the-line (MOL) dielectric layer as taught by Shen in order to enhance electrical isolation, reduce device failures, and to extend the devices lifetime.
Regarding claim 19. Kannan as modified discloses at least one transistor located adjacent to the d-fuse structure, wherein the at least one transistor is electrically connected to another frontside metal line of the BEOL structure ([0038, 0044], figure 5 and figure 8 annotated above, at least one transistor #807 is located adjacent to the d-fuse structure #803/f1/fml, and the transistor #807 is electrically connected to another frontside metal line #819 (the metal layer #819 is part of the frontside metal line #fml)).
Claims 2-3 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kannan et al. (US-20160225679-A1 referred as Kannan) and Shen et al. (US-20220285434-A1 referred as Shen) in further view of Lee et al. (US-6100116-A referred as Lee).
Regarding claim 2 and claim 3. Kannan as modified lacks
[claim 2] wherein the plurality of d-fuse vias is surrounded by a protective structure.
[claim 3] wherein the protective structure has a shape of a via or a bar.
[claim 13] wherein the electrically conductive fused region is surrounded by a protective structure.
[claim 14] wherein the protective structure has a shape of a via or a bar.
Lee discloses
[claim 2] wherein the plurality of d-fuse vias is surrounded by a protective structure ([col 1 lines 50-60], figure 3a, the plurality of d-fuse vias #74a are surrounded by a protective structure #78/70).
[claim 3] wherein the protective structure has a shape of a via or a bar ([col 1 lines 50-60], figure 3a, the protective structure #78/70 has a shape of a via).
[claim 13] wherein the electrically conductive fused region is surrounded by a protective structure ([col 1 lines 50-60], figure 3a, the electrically conductive fused region #74a are surrounded by a protective structure #78/70).
[claim 14] wherein the protective structure has a shape of a via or a bar ([col 1 lines 50-60], figure 3a, the protective structure #78/70 has a shape of a via).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kannan as modified to include wherein the plurality of d-fuse vias is surrounded by a protective structure as taught by Shen in order to protect the device from unwanted sources, reduce interference, and to promote consistent electrical output.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kannan et al. (US-20160225679-A1 referred as Kannan) and Shen et al. (US-20220285434-A1 referred as Shen) in view of Jao (US-20070069330-A1).
Regarding claim 5. Kannan lacks wherein a pitch between each neighboring d-fuse via of the plurality of d-fuse vias is from 10 ųm or less.
Jao discloses wherein a pitch between each neighboring d-fuse via of the plurality of d-fuse vias is from 10 ųm or less ([0018], the pitch of each neighboring d-fuse #102a/102b/102c is 2.6 – 7.7 ųm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kannan as modified to include wherein a pitch between each neighboring d-fuse via of the plurality of d-fuse vias is from 10 ųm or less. as taught by Shen in order to promote higher wiring density in the device, improve backside power delivery, and to protect from fuse blow damage.
Claims 7-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kannan et al. (US-20160225679-A1 referred as Kannan) and Shen et al. (US-20220285434-A1 referred as Shen) in further view of Chung et al. (US-20250087646-A1 referred as Chung).
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Figure 1 annotated
Regarding claim 7, 8, 15, and 16, Kannan as modified lacks
[claim 7] wherein the frontside metal line is connected to alternating d-fuse vias of the plurality of d-fuse vias by frontside metal vias.
[claim 8] wherein the frontside metal vias are embedded in a frontside interlayer dielectric (ILD) and each frontside metal via lands on the MOL dielectric layer.
[claim 15] wherein the frontside metal line is electrically connected to electrically conductive fused region by frontside metal vias.
[claim 16] wherein the frontside metal vias are embedded in a frontside interlayer dielectric (ILD) and each frontside metal via lands on the MOL dielectric layer.
Chung discloses
[claim 7] wherein the frontside metal line is connected to alternating d-fuse vias of the plurality of d-fuse vias by frontside metal vias ([0046], figure 1 annotated above, the frontside metal line #RT4 is connected to alternating d-fuse vias #RT5 by frontside metal vias #503. Please note not all d-fuse vias #RT5 would be connected to the frontside metal via #503 as seen specifically to d-fuse vias #RT5a. Therefore the connection is alternating).
[claim 8] wherein the frontside metal vias are embedded in a frontside interlayer dielectric (ILD) and each frontside metal via lands on the MOL dielectric layer ([0045], figure 1 annotated above, the frontside metal vias #503 are embedded in a frontside interlayer dielectric #MD2, and each frontside metal via #503 lands directly on the MOL dielectric layer #IL5).
[claim 15] wherein the frontside metal line is electrically connected to electrically conductive fused region by frontside metal vias ([0046], figure 1, the frontside metal line #RT4 is connected to electrically conductive fused region #RT5 by frontside metal vias #503).
[claim 16] wherein the frontside metal vias are embedded in a frontside interlayer dielectric (ILD) and each frontside metal via lands on the MOL dielectric layer ([0045], figure 1, the frontside metal vias #503 are embedded in a frontside interlayer dielectric #MD2, and each frontside metal via #503 lands directly on the MOL dielectric layer #IL5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kannan as modified to include wherein the frontside metal line has frontside metal vias within frontside interlayer dielectric as taught by Shen in order to distribute weight across the device, provide additional safety in the device, and to increase the devices lifetime.
Claims 9-10 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kannan et al. (US-20160225679-A1 referred as Kannan) and Shen et al. (US-20220285434-A1 referred as Shen) in further view of Chang et al. (US-20100270676-A1 referred as Chang).
Regarding claim 9, 10, 17, and 18. Kannan as modified lacks
[claim 9] wherein the backside power distribution network metal line is connected to alternating d-fuse vias of the plurality of d-fuse vias by backside power rails.
[claim 10] wherein the backside power rails are embedded in a backside ILD layer, and each backside power rail lands on a surface of the shallow trench dielectric structure.
[claim 17] wherein the backside power distribution network metal line is electrically connected to the electrically conductive fused region by backside power rails.
[claim 18] wherein the backside power rails are embedded in a backside ILD layer, and each backside power rail lands on a surface of the shallow trench dielectric structure.
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Figure 6 annotated
Chang discloses
[claim 9] wherein the backside power distribution network metal line is connected to alternating d-fuse vias of the plurality of d-fuse vias by backside power rails ([0060, 0080], the backside distribution network metal line #38 is connected to alternating d-fuse vias #60 by backside power rails #40. Please note not all d-fuse vias #60 would be connected to the backside power rails #40 as seen specifically in the pathway #40a above. Therefore the connection is alternating).
[claim 10] wherein the backside power rails are embedded in a backside ILD layer, and each backside power rail lands on a surface of the shallow trench dielectric structure ([0078], figure 6 annotated above, the backside power rails #40 are embedded in a backside ILD layer #45. The backside power rails #40 would land on the surface of the shallow trench dielectric structure #55 once bonded. As described in [0078] and illustrated, since there is more backside rails #40 than d-fuse vias #60 by 17 to 8, the backside rails #40 would in fact have additional surface area which would partly land on the surface of the shallow trench dielectric structure #55 (e.g. could be clearly seen at the path #40a above)).
[claim 17] wherein the backside power distribution network metal line is electrically connected to the electrically conductive fused region by backside power rails ([0060, 0080], the backside distribution network metal line #38 is connected to electrically conductive fused region #60 by backside power rails #40).
[claim 18] wherein the backside power rails are embedded in a backside ILD layer, and each backside power rail lands on a surface of the shallow trench dielectric structure ([0078], figure 6 annotated above, the backside power rails #40 are embedded in a backside ILD layer #45. The backside power rails #40 would land on the surface of the shallow trench dielectric structure #55 once bonded. As described in [0078] and illustrated, since there is more backside rails #40 than electrically conductive fused region #60 by 17 to 8, the backside rails #40 would in fact have additional surface area which would partly land on the surface of the shallow trench dielectric structure #55 (e.g. could be clearly seen at the path #40a above)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kannan as modified to include wherein the backside power distribution network metal line has a backside power rail within a backside ILD layer as taught by Shen in order to provide additional stability in the device, ensure the circuitry is within insulation, and to reduce future device failures.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants disclosure includes Chang et al. (US-20260013094-A1) and Medikonda et al. (US-20250118660-A1) for teaching the backside power rails, frontside metal lines, and fuses.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
