Prosecution Insights
Last updated: July 17, 2026
Application No. 18/668,954

METHOD OF TRANSFERRING LIGHT EMITTING CHIP, LIGHT EMITTING STRUCTURE AND DISPLAY PANEL

Non-Final OA §102§103
Filed
May 20, 2024
Priority
Jul 04, 2023 — CN 202310811963.9
Examiner
KLEIN, JORDAN M
Art Unit
Tech Center
Assignee
HKC Corporation Limited
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
460 granted / 538 resolved
+25.5% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
18 currently pending
Career history
558
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
86.7%
+46.7% vs TC avg
§102
10.1%
-29.9% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the applicant's application filed May 20th, 2024. In virtue of this communication, claims 1-20 are currently presented in the instant application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeya (US 2019/0393198 A1). With respect to claim 12, Takeya teaches a light emitting structure in Figs. 2A-2I with Fig. 1A teaching overlapping subject matter, comprising a light emitting transfer structure, wherein the light emitting transfer structure comprises a transfer film layer 110, an electrode fixing structure S and a light emitting chip 120 (see Fig. 2A, 2H, and paragraphs 71, 72, 79, 80); wherein the electrode fixing structure S is provided on the transfer film layer 110, the transfer film layer 110 is provided with a through-wire hole (via-hole) close to the electrode fixing structure S, and an electrode of the light emitting chip 120 is connected to the electrode fixing structure S (see Fig. 2H and paragraphs 79, 80); wherein the light emitting structure further comprises a driving backplane 59, a binding-point electrode (bottom of 132’, 134’) is provided on a surface of the driving backplane 59, the light emitting transfer structure is provided on the driving backplane 59, and the through-wire hole (via-hole) corresponds to the binding-point electrode (bottom of 132’, 134’) of the driving backplane 59 (see 2H, 2I, and paragraphs 79-81); and wherein the light emitting structure further comprises a connection wire (132’ and 134’ in via-hole), the connection wire (132’ and 134’ in via-hole) is provided in the through-wire hole (via-hole), an end of the connection wire is connected to the binding-point electrode (bottom of 132’, 134’) and another end of the connection wire is connected to the electrode fixing structure S (see Figs. 2H, 2I, and paragraphs 79-81). With respect to claim 15, Takeya teaches the light emitting structure according to claim 12, wherein the electrode fixing structure S comprises an anode fixing portion (where S connects to 37) and a cathode fixing portion (where S connects to 35) spaced from each other, two through-wire holes comprising an anode through-wire hole (134’ in via-hole) and a cathode through-wire hole (132’ in via-hole), the anode through-wire hole is opened on a side of the anode fixing portion (where S connects to 37) away from the cathode fixing portion (where S connects to 35), the cathode through-wire hole is opened on a side of the cathode through-wire hole away from the anode fixing portion (where S connects to 37), the anode through-wire hole (134’ in via-hole) and the cathode through-wire hole (132’ in via-hole) are provided respectively at both sides of the light emitting chip 120 (see Figs. 1A, 2H, 2I, and paragraphs 53, 59, 80; p-type means positive anode and n-type means negative cathode). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 8-10, and 16 is rejected under 35 U.S.C. 103 as being unpatentable over Takeya (US 2019/0393198 A1). With respect to claim 1, Takeya discloses a method of transferring a light emitting chip 120 in Figs. 2A-2I with Fig .1A teaching overlapping subject matter, comprising: forming a light emitting chip 120 on a surface of a growth substrate 57 (see Figs. 2F, 2G and paragraphs 78, 79); forming a transfer film layer 110 on a transient substrate (buffer layer) (see Fig. 2H and paragraphs 79-81); forming an electrode fixing structure S on a side of the transfer film layer 110 away from the transient substrate (buffer), and opening a through-wire hole (via-hole) in the transfer film layer 110 adjacent to the electrode fixing structure S (see Fig. 2H and paragraphs 79-81); making the growth substrate 57 opposite to the transient substrate (buffer layer), to make an electrode of the light emitting chip 120 on the growth substrate 57 connect to the electrode fixing structure S on the transient substrate (buffer layer) (see Figs. 2H, 2I, and paragraphs 79-81); stripping off the growth substrate 57 to form a light emitting transfer structure (see Figs. 2H, 2I and paragraphs 79-81); making the light emitting transfer structure opposite to a driving backplane 59, to make a through-wire hole (via-hole) in the light emitting transfer structure correspond to a binding-point electrode (bottom of 132’, 134’) on the driving backplane 59 (see Figs. 2H, 2I, and paragraphs 79-81); and forming a connection wire (132’ and 134’ in via-hole), wherein a portion of the connection wire (132’ and 134’ in via-hole) is connected to the binding-point electrode (bottom of 132’ and 134’) through the through-wire hole (via-hole), and another portion of the connection wire is connected to the electrode fixing structure S (see Figs. 2H, 2I, and paragraphs 79-81). Takeya does not explicitly disclose stripping off at least a portion of the transient substrate. However, Takeya discloses that 132’ and 134’ are disposed on the lower surface of 110 and that the transient substrate (buffer) is disposed between 110 and 59 (see paragraphs 79, 81). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display panel would comprise stripping off at least a portion of the transient substrate because such a stripping off of the transient substrate (buffer) would be required to allow the first and second substrate electrodes 132’ and 134’ to be formed on the lower surface of 110 (see MPEP 2144 I). With respect to claim 8, Takeya discloses the method of transferring the light emitting chip according to claim 1, wherein making the growth substrate 57 opposite to the transient substrate (buffer layer) means that the light emitting chip 120 and the electrode fixing structure S are opposite to each other, and the electrode of the light emitting chip 120 is directly faced to the electrode fixing structure S (see Figs. 1A, 2H, 2I, and paragraphs 53, 59, 79-81). With respect to claim 9, Takeya discloses the method of transferring the light emitting chip according to claim 1, wherein electrodes of the light emitting chip 120 comprises an anode 37 and a cathode 35, and two through-wire holes (via-hole) are provided; two binding-point electrodes (bottom of 132’ and 134’) on the driving backplane 59 are provided, one of two binding-point electrodes is configured for providing an electrical signal to the anode (where S connects to 37) of the light emitting chip 120 and the other of the two binding-point electrodes is configured for providing electrical signals to the cathode (where S connects to 35) of the light emitting chip 120 (see Figs. 1A, 2H, 2I, and paragraphs 53, 59, 80; p-type means positive anode and n-type means negative cathode). With respect to claim 10, Takeya discloses the method of transferring the light emitting chip according to claim 9, wherein the electrode fixing structure S comprises an anode fixing portion (where S connects to 37) and a cathode fixing portion (where S connects to 37) spaced from each other, the two through-wire holes comprise an anode through-wire hole (134’ in via-hole) and a cathode through-wire hole (132’ in via-hole), the anode through-wire hole is opened on a side of the anode fixing portion (where S connects to 37) away from the cathode fixing portion (where S connects to 35), the cathode through-wire hole is opened on a side of the cathode through-wire hole away from the anode fixing portion (where S connects to 37), the anode through-wire hole (134’ in via-hole) and the cathode through-wire hole (132’ in via-hole) are provided respectively at both sides of the light emitting chip 120 (see Figs. 1A, 2H, 2I, and paragraphs 53, 59, 80; p-type means positive anode and n-type means negative cathode).. With respect to claim 16, Takeya discloses a display panel in Figs. 2A-2I with Fig. 1A teaching overlapping subject matter, comprising a light emitting chip 120 and a driving backplane 59, wherein a method of transferring the light emitting chip 120 is used by the display panel to transfer the light emitting chip 120 to the driving backplane 59 (see Figs. 2A, 2H, 2I and paragraphs 71, 72, 79-81), and paragraphs ; wherein the method comprises: forming a light emitting chip 120 on a surface of a growth substrate 57 (see Figs. 2F, 2G and paragraphs 78, 79); forming a transfer film layer 110 on a transient substrate (buffer layer) (see Fig. 2H and paragraphs 79-81); forming an electrode fixing structure S on a side of the transfer film 110 layer away from the transient substrate (buffer), and opening a through-wire hole (via-hole) in the transfer film layer 110 adjacent to the electrode fixing structure S (see Fig. 2H and paragraphs 79-81); making the growth substrate 57 opposite to the transient substrate (buffer layer), to make an electrode of the light emitting chip 120 on the growth substrate 57 connect to the electrode fixing structure S on the transient substrate (buffer layer) (see Figs. 2H, 2I, and paragraphs 79-81); stripping off the growth substrate 57 to form a light emitting transfer structure (see Figs. 2H, 2I, and paragraphs 79-81); making the light emitting transfer structure opposite to a driving backplane 59, to make a through-wire hole (via-hole) in the light emitting transfer structure correspond to a binding-point electrode (bottom of 132’, 134’) on the driving backplane 59 (see Figs. 2H, 2I, and paragraphs 79-81); and forming a connection wire (132’ and 134’ in via-hole), wherein a portion of the connection wire (132’ and 134’ in via-hole) is connected to the binding-point electrode (bottom of 132’, 134’) through the through-wire hole (via-hole), and another portion of the connection wire is connected to the electrode fixing structure S (see Figs. 2H, 2I, and paragraphs 79-81). Takeya does not explicitly disclose stripping off at least a portion of the transient substrate. However, Takeya discloses that 132’ and 134’ are disposed on the lower surface of 110 and that the transient substrate (buffer) is disposed between 110 and 59 (see paragraphs 79, 81). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display panel would comprise stripping off at least a portion of the transient substrate because such a stripping off of the transient substrate (buffer) would be required to allow the first and second substrate electrodes 132’ and 134’ to be formed on the lower surface of 110 (see MPEP 2144 I). Allowable Subject Matter Claims 2-7, 11, 13, 14, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest: wherein the forming the electrode fixing structure on the side of the transfer film layer away from the transient substrate comprises: providing a conductive layer on a surface of the transfer film layer, and providing a conductive adhesive on a side of the conductive layer away from the transfer film layer; wherein the electrode of the light emitting chip is connected to the conductive layer through the conductive adhesive, as called for in claim 2 (claims 3 and 11 depend from claim 2); wherein the opening the through-wire hole in the transfer film layer adjacent to the electrode fixing structure comprises: providing a stripped-off layer on a surface of the transfer film layer, and providing an etching blocking layer on a side of the stripped-off layer away from the transfer film layer, wherein the stripped-off layer covers the electrode fixing structure; opening an etching hole in the etching blocking layer, and opening an etching channel in the stripped-off layer corresponding to the etching hole, wherein a positive projection of the etching hole on the transfer film layer is located outside a positive projection of the electrode fixing structure on the transfer film layer; etching the transfer film layer through the etching hole and the etching channel to form the through-wire hole; and stripping off the stripped-off layer to remove the etching blocking layer, as called for in claim 4; wherein before the transferring the light emitting transfer structure to the driving backplane comprises: providing an adhesive layer on a surface of the driving backplane to adhesively fix the transfer film layer to the driving backplane, as called for in claim 5 (claim 6 depends from claim 5); wherein the light emitting chip comprises an epitaxial layer and electrodes, the forming the light emitting chip on the surface of the growth substrate comprises: forming the epitaxial layer on the surface of the growth substrate, and forming the electrodes on a top of the epitaxial layer, as called for in claim 7; wherein the light emitting transfer structure comprises a transient substrate provided between the transfer film layer and the driving backplane, and the transient substrate is provided with a through-hole corresponding to the through-wire hole, as called for in claim 13; wherein the light emitting structure comprises a dielectric layer provided on the driving backplane, and a positive projection of the light emitting chip on the driving backplane is located within a positive projection of the dielectric layer on the driving backplane, as called for in claim 14; wherein the forming the electrode fixing structure on the side of the transfer film layer away from the transient substrate comprises: providing a conductive layer on a surface of the transfer film layer, and providing a conductive adhesive on a side of the conductive layer away from the transfer film layer; wherein the electrode of the light emitting chip is connected to the conductive layer through the conductive adhesive, as called for in claim 17 (claim 18 depends from claim 17); wherein the opening the through-wire hole in the transfer film layer adjacent to the electrode fixing structure comprises: providing a stripped-off layer on a surface of the transfer film layer, and providing an etching blocking layer on a side of the stripped-off layer away from the transfer film layer, wherein the stripped-off layer covers the electrode fixing structure; opening an etching hole in the etching blocking layer, and opening an etching channel in the stripped-off layer corresponding to the etching hole, wherein a positive projection of the etching hole on the transfer film layer is located outside a positive projection of the electrode fixing structure on the transfer film layer; etching the transfer film layer through the etching hole and the etching channel to form the through-wire hole; and stripping off the stripped-off layer to remove the etching blocking layer, as called for in claim 19; wherein before the transferring the light emitting transfer structure to the driving backplane comprises: providing an adhesive layer on a surface of the driving backplane to adhesively fix the transfer film layer to the driving backplane, as called for in claim 20. Inquiry Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.M.K/Examiner, Art Unit 2893 /SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

May 20, 2024
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.7%)
2y 5m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allowance rate.

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