Nb b DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Applicant’s IDS submitted on 5/20/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ELECTRONIC DEVICE USED FOR INTEGRATING MULTIPLE CONTACTS AND FIRST ELECTRONIC COMPONENT, COMPRISES SUBSTRATE WITH FIRST CONTACT WITH FIRST AND SECOND EXTERNAL TERMINALS, SECOND CONTACT WITH EXTERNAL TERMINALS, AND THIRD CONTACT WITH EXTERNAL TERMINAL
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6-7, 9-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon, US 20250285931 A1, hereafter Jeon.
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Regarding independent claim 1, Jeon discloses the following limitations:
An electronic device, comprising:
a substrate comprising:
a first contact (Jeon, Figure 5, thin leadframe 108 and thick leadframe 102 [0032], of electronic package 100, not including leads 108A and 108B) comprising a first contact top side, a first contact bottom side opposite to the first contact top side, a first contact first lateral side, and a first contact second lateral side opposite to the first contact first lateral side (Shown, Figure 2 and Figure 5);
a first contact first external terminal coupled to and extending outward from the first contact first lateral side (Jeon, Figure 5, lead 108A, including the portion that is perpendicular to the first contact to the external end);
a first contact second external terminal coupled to and extending outward from the first contact first lateral side (Jeon, Figure 2, lead 108B, the portion that is perpendicular to the first contact, to the external end), wherein the first contact second external terminal and the first contact first external terminal are separated by a gap (Jeon, Figure 5, shows a gap between leads 108A and 108B);
a second contact proximate to and laterally separated from the first contact second lateral side (Jeon, Figure 5, wirebond pad 524);
a second contact first external terminal coupled to and extending outward from the second contact (Jeon, Figure 5, pin 106, top pin connected to 524);
a second contact second external terminal coupled to and extending outward from the second contact (Jeon, Figure 5, pin 106, second pin connected to 524);
a third contact proximate to and laterally separated from the first contact second lateral side (Jeon, Figure 5, gate bonding pad 542); and
a third contact first external terminal coupled to and extending outward from the third contact (Jeon, Figure 5, gate lead 546);
a first electronic component (Jeon, Figure 5, semiconductor die 214) comprising a first electronic component top side (Jeon, Figure 3, where the top side of semiconductor die 214 is defined as the one wirebond 216 contacts and [0035] which discloses that the drain terminal is the bottom surface) and a first electronic component bottom side opposite to the first electronic component top side, wherein the first electronic component bottom side is coupled to the first contact top side (Jeon, Figure 3, of electronic package 100, shows thick leadframe 102 electrically coupling the top of thin leadframe 108A to the bottom side of semiconductor die 214), a first part of the first electronic component top side is electrically coupled to the second contact (Jeong, Figure 5, bonding pad 540 is electrically connected to semiconductor die 214 and to wirebond pad 524), and a second part of the first electronic component is electrically coupled to the third contact (Jeon, Figure 5, semiconductor die 214 is electrically connected to gate bonding pad 542); and
an encapsulant covering the substrate and the first electronic component (Jeon, Figure 3, body 104 and [0004] discloses an electrically insulative encapsulant at least partially encapsulating the metal plate, the semiconductor transistor, the drain lead, the source lead, the source conductor, the gate lead and the gate conductor”);
wherein:
the encapsulant comprises an encapsulant top side, an encapsulant bottom side opposite to the encapsulant top side, and an encapsulant lateral side (Jeon, Figure 1 and Figure 3, body 104);
the first contact first external terminal (Jeon, Figure 1, lead 108A), the first contact second external terminal (Jeon, Figure 1, lead 108B), the second contact first external terminal (Jeon, Figure 1, pin 106, far right), the second contact second external terminal (Jeon, Figure 1, pin 106, next to far right), and the third contact first external terminal are exposed from the encapsulant (Jeon, Figure 1, pin 106, far left (corresponding to Figure 5, gate lead 546));
the first contact bottom side is exposed from the encapsulant top side (Figure 3, thick leadframe 102 (attached to thin leadframe 108), bottom side is exposed from body 104); and
Jeon does not show or describe the relationship between the encapsulant and the gap between leads 108A and 108B and therefore fails to disclose the following limitation:
the encapsulant covers a portion of the gap proximate to the first contact first lateral side.
Jeon teaches to encapsulate the semiconductor die, wirebonds and leadframes but lack teaching if the encapsulant covers a portion of the gap proximate to the first contact first lateral side. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have covered the gap because doing so would protect the side of the thin leadframe in the gap, and improve the sealing of the device as it would reduce the length of openings through the encapsulant.
Regarding claim 2, Jeon discloses the following limitations:
The electronic device of claim 1, wherein:
the first contact first external terminal comprises (Jeon, Figure 5, lead 108A, the portion that is perpendicular to thin leadframe to the end away from the first contact):
a first projection extending outward from the first contact first lateral side (Jeon, Figure 5, lead 108A, the portion that is perpendicular to the first contact); and
a first extension extending outward from the first projection in a first direction (Jeon, Figure 5, lead 108A, the portion from the portion perpendicular to the first contact to the external end); and
the first contact second external terminal comprises (Jeon, Figure 5, lead 108B, the portion that is perpendicular to thin leadframe to the end away from the first contact):
a second projection extending outward from the first contact first lateral side and separated from the first projection by the gap (Jeon, Figure 5, lead 108B, the portion that is perpendicular to the first contact); and
a second extension extending outward from the second projection in a second direction different than the first direction (Jeon, Figure 5, lead 108B, the portion from the portion perpendicular to the first contact to the external end).
Regarding claim 3, Jeon discloses the following limitations:
The electronic device of claim 2, wherein:
the first extension extends from the first projection in a direction towards the encapsulant bottom side (Jeon, figure 3, lead 108A extends toward the bottom side of body 104); and
the second extension extends from the second projection in the direction towards the encapsulant bottom side (Jeon, figure 3, lead 108B extends toward the bottom side of body 104).
Regarding claim 6, Jeon discloses the following limitations:
The electronic device of claim 2, wherein the first direction is opposite the second direction (Jeon, Figure 1, leads 108A, 108B extending in opposite directions).
Regarding claim 7, Jeon discloses the following limitations:
The electronic device of claim 1, wherein:
the first contact (Joen, Figure 3, lead 108A and thick leadframe 102) resides on a first plane (Jeon, Figure 3, where the first plane is the top of 102);
the second contact and the third contact (Joen, Figure 3, pin 106) reside on a second plane (Jeon, Figure 3, where the second plane is the top of 106); and
the first plane is elevated above the second plane in a cross-sectional view (Jeon, Figure 3, the top of 102 is above the top of 106).
Regarding claim 9, Jeon discloses the following limitations:
The electronic device of claim 1, wherein:
the second contact first external terminal (Jeon, Figure 5, pin 106, top pin connected to 524) and the second contact second external terminal (Jeon, Figure 5, pin 106, second pin connected to 524) extend from the second contact a direction towards the encapsulant bottom side (Jeon, Figure 1 and Figure 5, show all pins 106 extend in the direction of the encapsulant bottom side); and
the third contact first external terminal (Jeon, Figure 5, gate lead 546) extends from the third contact in the direction towards the encapsulant bottom side (Jeon, Figure 1 shows pins 106 extend in the direction of the encapsulant bottom side, and Figure 5 shows that 546 is one of the pins in Figure 1).
Regarding claim 10, Jeon discloses the following limitations:
The electronic device of claim 1, further comprising:
a fourth contact (Jeon, Figure 5, unlabeled square contact above 542); and
a fourth contact first external terminal coupled to and extending outward from the fourth contact (Jeon, Figure 5, Kelvin source lead 544, one of pins 106);
wherein:
a third part of the first electronic component top side is electrically coupled to the fourth contact (Jeon, Figure 5, unlabeled square contact above 542, is separate from 524/540, and 542); and
the fourth contact first external terminal is exposed from the encapsulant (Jeon, Figure 1, shows the seven pins 106 of Figure 5 exposed from the encapsulant).
Regarding independent claim 19, Jeon discloses the following limitations:
A method of manufacturing an electronic device, comprising:
providing a substrate comprising:
a first contact (Jeon, Figure 5, thin leadframe 108 and thick leadframe 102 [0032], of electronic package 100, not including leads 108A and 108B) comprising a first contact top side, a first contact bottom side opposite to the first contact top side, a first contact first lateral side, and a first contact second lateral side opposite to the first contact first lateral side (Shown, Figure 2 and Figure 5);
a first contact first external terminal coupled to and extending outward from the first contact first lateral side (Jeon, Figure 5, lead 108A, including the portion that is perpendicular to the first contact to the external end);
a first contact second external terminal coupled to and extending outward from the first contact first lateral side (Jeon, Figure 2, lead 108B, the portion that is perpendicular to the first contact, to the external end), wherein the first contact second external terminal and the first contact first external terminal are separated by a gap (Jeon, Figure 5, shows a gap between leads 108A and 108B);
a second contact proximate to and laterally separated from the first contact second lateral side (Jeon, Figure 5, wirebond pad 524);
a second contact first external terminal coupled to and extending outward from the second contact (Jeon, Figure 5, pin 106, top pin connected to 524);
a second contact second external terminal coupled to and extending outward from the second contact (Jeon, Figure 5, pin 106, second pin connected to 524);
a third contact proximate to and laterally separated from the first contact second lateral side (Jeon, Figure 5, gate bonding pad 542); and
a third contact first external terminal coupled to and extending outward from the third contact (Jeon, Figure 5, gate lead 546);
providing a first electronic component (Jeon, Figure 5, semiconductor die 214) comprising a first electronic component top side (Jeon, Figure 3, where the top side of semiconductor die 214 is defined as the one wirebond 216 contacts and [0035] which discloses that the drain terminal is the bottom surface) and a first electronic component bottom side opposite to the first electronic component top side, wherein the first electronic component bottom side is coupled to the first contact top side (Jeon, Figure 3, of electronic package 100, shows thick leadframe 102 electrically coupling the top of thin leadframe 108A to the bottom side of semiconductor die 214), a first part of the first electronic component top side is electrically coupled to the second contact (Jeong, Figure 5, bonding pad 540 is electrically connected to semiconductor die 214 and to wirebond pad 524), and a second part of the first electronic component is electrically coupled to the third contact (Jeon, Figure 5, semiconductor die 214 is electrically connected to gate bonding pad 542); and
providing an encapsulant covering the substrate and the first electronic component (Jeon, Figure 3, body 104 and [0004] discloses an electrically insulative encapsulant at least partially encapsulating the metal plate, the semiconductor transistor, the drain lead, the source lead, the source conductor, the gate lead and the gate conductor”);
wherein:
the encapsulant comprises an encapsulant top side, an encapsulant bottom side opposite to the encapsulant top side, and an encapsulant lateral side (Jeon, Figure 1 and Figure 3, body 104);
the first contact first external terminal (Jeon, Figure 1, lead 108A), the first contact second external terminal (Jeon, Figure 1, lead 108B), the second contact first external terminal (Jeon, Figure 1, pin 106, far right), the second contact second external terminal (Jeon, Figure 1, pin 106, next to far right), and the third contact first external terminal are exposed from the encapsulant (Jeon, Figure 1, pin 106, far left (corresponding to Figure 5, gate lead 546));
the first contact bottom side is exposed from the encapsulant top side (Figure 3, thick leadframe 102 (attached to thin leadframe 108), bottom side is exposed from body 104); and
Jeon does not show or describe the relationship between the encapsulant and the gap between leads 108A and 108B and therefore fails to disclose the following limitation:
the encapsulant covers a portion of the gap proximate to the first contact first lateral side.
Jeon teaches to encapsulate the semiconductor die, wirebonds and leadframes but lack teaching if the encapsulant covers a portion of the gap proximate to the first contact first lateral side. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have covered the gap because doing so would protect the side of the thin leadframe in the gap, and improve the sealing of the device as it would reduce the length of openings through the encapsulant.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon, US 20250285931 A1, hereafter Jeon in view of Gan et al., US 20210391246 A1, hereafter Gan.
Regarding independent claim 11, Jeon discloses the following limitations:
An electronic device (Jeon, Figure 2, electronic package 100 containing semiconductor die 214), comprising:
a first modular electronic package (Jeon, Figure 1, electronic package 100) comprising:
a first substrate (Jeon, Figure 1, thin leadframe 108 and thick leadframe 102) comprising:
a first current carrying contact (Jeon, Figure 5, thin leadframe 108 and thick leadframe 102 [0032], of electronic package 100, not including leads 108A and 108B, which is a contact because it contacts the semiconductor die 214) comprising a first side, a second side opposite to the first side, a first lateral side, and a second lateral side opposite to the first lateral side;
a first external terminal coupled to and extending from the first current carrying contact (Jeon, Figure 5, lead 108A, including the portion that is perpendicular to the first contact to the external end);
a second current carrying contact (Jeon, Figure 5, source bonding pad 540);
a second external terminal coupled to and extending from the second current carrying contact (Jeon, Figure 5, pin 106, top pin, one of five common source leads 548);
a first control contact (Jeon, Figure 5, unlabeled square contact above 542);
a first control contact external terminal coupled to and extending from the first control contact (Jeon, Figure 5, Kelvin source lead 544, one of pins 106);
a second control contact (Jeon, Figure 5, gate bonding pad 542); and
second control contact external terminal coupled to and extending from the second control contact (Jeon, Figure 1, pin 106, gate lead 546);
a first electronic component (Jeon Figure 5, semiconductor die 214) comprising a first electronic component top side, a first electronic component bottom side opposite to the first electronic component bottom side, wherein the first electronic component bottom side is coupled to the first side of the first current carrying contact (Jeon, Figure 3, show semiconductor die 214 coupled to leadframe 102, so the side opposite wirebond 216 is the bottom side of 214, and the side of 102 adjacent to 214 is the first side of the current carrying contact 102/108), a first part of the first electronic component top side is coupled to the second current carrying contact (Jeon, Figure 5, shows source bonding pad 540 on 214 and wideband 216 attached to 542, making it the top side of 214), and a second part of the first electronic component top side is coupled to the first control contact (Jeon, Figure 5, unlabeled square contact above 542 on 214 and wideband 216 attached to 544, making it the top side of 214);
a first encapsulant covering the first substrate, the first electronic component (Jeon, Figure 1, body 104, disclosed as an electrically insulative material, such as a resin, formed by molding in [0026] and Figure 3, shows 104 covering the semiconductor die 214, which includes the electronic component);
wherein:
the first encapsulant comprises a first encapsulant top side, a first encapsulant bottom side opposite to the first encapsulant top side, a first encapsulant first lateral side, and a first encapsulant second lateral side opposite to the first encapsulant first lateral side (Jeon, Figure 1 and Figure 3);
the second side of the first current carrying contact is exposed from the first
encapsulant top side (Jeon, Figure 3, thick leadframe 102 where attached to 108 is exposed from body 104);
the first external terminal is exposed from the first encapsulant at the first encapsulant first lateral side (Jeon, Figure 1, lead 108A is exposed form body 104 from the left side of the device); and
the second external terminal, the first control contact external terminal, and the second control contact external terminal are exposed from the first encapsulant at the first encapsulant second lateral side (Jeon, Figure 1, pins 106 (including common source leads 548, gate lead 546, and Kelvin source lead 544) are exposed from the second lateral side of body 104).
Jeon fails to disclose the following limitations:
a second electronic component comprising a second electronic component top side and a second electronic component bottom side opposite to the second electronic component top side, wherein the second electronic component bottom side is coupled to the first side of the first current carrying contact, a first part of the second electronic component top side is coupled to the second current carrying contact, and a second part of the second electronic component top side is coupled to the second control contact; and
(the encapsulant covers) the second electronic component;
Gan discloses the following limitations:
a second electronic component (Gan, Figure 1, two semiconductor dies 104) comprising a second electronic component top side and a second electronic component bottom side opposite to the second electronic component top side, wherein the second electronic component bottom side is coupled to the first side of the first current carrying contact (Gan Figure 1, bottom side of 104 is connected to the leadframe, since the transistor of Gan are connected in parallel (disclosed in [0033], and shown in Figure 1) the similar contacts of the devices are connected together), a first part of the second electronic component top side is coupled to the second current carrying contact (Gan, Figure 1, second upper surface terminals 126 disclosed as sensing terminals [0033]), and a second part of the second electronic component top side is coupled to the second control contact (Gan, Figure 1, first upper surface terminals 124 disclosed as gate terminals [0033]); and
(the encapsulant covers) the second electronic component (Gan, Figure 2, encapsulant body 202 is shown covering both semiconductor dies 104);
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teaching of Gan to use two transistors devices connected in parallel in the device of Jeon because such a combination would desirably allow the device to handle increased current as compared to a single transistor device, or improve reliability by providing a redundant transistor, allowing the device to continue functioning after one transistor fails.
Regarding claim 12, the combination of Jeon and Gan discloses the following limitations:
The electronic device of claim 11, wherein:
the first external terminal extends from the first current carrying contact toward the first encapsulant bottom side (Jeon, Figure 3, lead 108A extends toward the bottom side of body 104); and
the second external terminal extends from the second current carrying contact in a direction toward the first encapsulant bottom side (Jeon, Figure 1 and Figure 5, show all pins 106 extend in the direction of the encapsulant bottom side).
Regarding claim 13, the combination of Jeon and Gan discloses the following limitations:
The electronic device of claim 11, wherein the first external terminal comprises:
a first projection extending outward from the first current carrying contact (Jeon, Figure 5, lead 108A, the portion that is perpendicular to the first contact);
a first extension extending outward from the first projection in a first direction (Jeon, Figure 5, lead 108A, the portion that is perpendicular to the first contact);
a second projection extending outward from the first current carrying contact separated from the first projection by a gap (Jeon, Figure 5, lead 108B, the portion that is perpendicular to the first contact); and
a second extension extending outward from the second projection in a second direction different than the first direction (Jeon, Figure 5, lead 108B, the portion from the portion perpendicular to the first contact to the external end, and Figure 5 shows that 108A and 108B extend in opposite directions);
wherein:
the first extension extends from the first projection in a direction towards the first encapsulant bottom side (Jeon, figure 3, lead 108A extends toward the bottom side of body 104); and
the second extension extends from the second projection in the direction towards the first encapsulant bottom side (Jeon, figure 3, lead 108B extends toward the bottom side of body 104).
Claims 4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon as applied to claim 2 and 19 above, and further in view of Kelkar et al., US 20130181332 A1, hereafter Kelkar.
Regarding claim 4, Jeon fails to disclose the following limitations:
The electronic device of claim 2, further comprising:
chamfers in the first contact first lateral side, a lateral side of the first projection and a lateral side of the second projection, wherein the encapsulant covers the chamfers.
Regarding claim 4, Kelkar discloses the following limitations:
chamfers in the first contact first lateral side, a lateral side of the first projection and a lateral side of the second projection, wherein the encapsulant covers the chamfers (Kelkar, Figure 4, and [0021] discloses that beveling the sharp corners of the cut outs 132a and 132b improves current conduction and prevents current congregation or sharp electric fields).
It would have been obvious tone one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Kelkar to bevel the sharp corners in the leadframe of Jeon because Kelkar discloses that doing so improves the device by improving current conduction and preventing current congregation or sharp electric fields.
Regarding claim 20, Jeon discloses the following limitations:
The method of claim 19, wherein:
providing the substrate comprises:
providing the first contact first external terminal (Jeon, Figure 5, lead 108A) comprising:
a first projection extending outward from the first contact first lateral side (Jeon, Figure 5, lead 108A, the portion that is perpendicular to the first contact); and
a first extension extending outward from the first projection in a first direction (Jeon, Figure 5, lead 108A, the portion that is perpendicular to the first contact); and
providing the first contact second external terminal (Jeon, Figure 5, lead 108B) comprising:
a second projection extending outward from the first contact first lateral side and separated from the first projection by the gap (Jeon, Figure 5, lead 108B, the portion that is perpendicular to the first contact, and separated from 108A by a gap); and
a second extension extending outward from the second projection in a second direction different than the first direction (Jeon, Figure 5, lead 108B, the portion from the portion perpendicular to the first contact to the external end, and Figure 5 shows that 108A and 108B extend in opposite directions);
the first extension extends from the first projection in a direction towards the encapsulant bottom side (Jeon, figure 3, lead 108A extends toward the bottom side of body 104);
the second extension extends from the second projection in the direction towards the encapsulant bottom side (Jeon, figure 3, lead 108B extends toward the bottom side of body 104);
Jeon fails to discloses the following limitations:
providing chamfers in the substrate;
the chamfers are provided in the first contact first lateral side, a lateral side of the first projection and a lateral side of the second projection; and
providing the encapsulant comprises providing the encapsulant covering the chamfers.
Kelkar discloses the following limitation:
providing chamfers in the substrate (Kelkar, Figure 4, and [0021] discloses that beveling the sharp corners of the cut outs 132a and 132b improves current conduction and prevents current congregation or sharp electric fields);
the chamfers are provided in the first contact first lateral side, a lateral side of the first projection and a lateral side of the second projection (Kelkar, Figure 4, and [0021] discloses that beveling the sharp corners of the cut outs 132a and 132b improves current conduction and prevents current congregation or sharp electric fields); and
providing the encapsulant comprises providing the encapsulant covering the chamfers (Kelkar, Figure 8, shows the chamfered regions withing the dotted region of the encapsulant).
It would have been obvious tone one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Kelkar to bevel the sharp corners in the headframe of Jeon because Kelkar discloses that doing so improves the device by improving current conduction and preventing current congregation or sharp electric fields. Furthermore, it would have been obvious to have covered the chamfered regions with the encapsulant because doing so is taught by Kelkar and would provide support for the contacts.
Claims 5, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon as applied to claim 1, and 2 above, and further in view of Loh et al., US 20080012036 A1, hereafter Loh.
Regarding claim 5, Jeon fails to discloses the following limitations:
The electronic device of claim 2, further comprising:
grooves that extend partially into surfaces of the first projection and the second projection, wherein the encapsulant covers the grooves
Regarding claim 5, Loh discloses the following limitations:
grooves that extend partially into surfaces of the first projection and the second projection, wherein the encapsulant covers the grooves (Loh, Figure 10C, leak barriers 408, disclosed in [0110] as grooves that may be etched and/or stamped into the leadframe 400, which are then covered by package body 420 in Figure 11B).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Loh to the device of Jeon and to therefore have formed grooves in the electrodes and then covered the grooves with encapsulant. Doing so it taught by Loh to provide three-dimensional surface for bonding the package body and provide a longer path through which potential leaks would have to travel to get to the device.
Regarding claim 8, Jeon and Loh discloses the following limitations:
The electronic device of claim 1, further comprising:
a groove that extends partially into the second contact between the second contact first external terminal and the second contact second external terminal, wherein the encapsulant covers the groove (Loh, Figure 10C, leak barriers 408, disclosed in [0110] as grooves that may be etched and/or stamped into the leadframe 400, which are then covered by package body 420 in Figure 11B).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon and Gan as applied to claim 11 above, and further in view of Loh et al., US 20080012036 A1, hereafter Loh.
Regarding claim 15, the combination of Jeon and Loh discloses the following limitations:
The electronic device of claim 11, further comprising:
grooves extending partially into the second current carrying contact (Loh, Figure 10C, leak barriers 408, disclosed in [0110] as grooves that may be etched and/or stamped into the leadframe 400, which are then covered by package body 420 in Figure 11B);
wherein:
the second external terminal is one of a plurality of second external terminals coupled to and extending from the second current carrying contact (Jeon, Figure 5, multiple pins 106 are attached to 540 by wirebonds 216);
the grooves are interposed between adjacent ones of the plurality of second external terminals (Loh, Figure 10C, leak barriers 408, disclosed in [0110] as grooves that may be etched and/or stamped into the leadframe 400, which are then covered by package body 420 in Figure 11B); and
the first encapsulant covers the grooves (Loh, Figure 11B, package body 420 covers leak barriers 408 of Figure 10C).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Loh to the device of Jeon and to therefore have formed grooves in the electrodes and then covered the grooves with encapsulant. Doing so it taught by Loh to provide three-dimensional surface for bonding the package body and provide a longer path through which potential leaks would have to travel to get to the device.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon and Gan as applied to claim 13 above, and further in view of Kelkar et al., US 20130181332 A1, hereafter Kelkar and Loh et al., US 20080012036 A1, hereafter Loh.
Regarding claim 14, Jeon fails to discloses the following limitations:
The electronic device of claim 13, further comprising:
chamfers in the first lateral side, a lateral side of the first projection and a lateral side of the second projection; and
grooves that extend partially into surfaces of the first projection and the second projection;
wherein:
the first encapsulant covers the chamfers and the grooves.
Kelkar discloses the following limitations:
chamfers in the first lateral side, a lateral side of the first projection and a lateral side of the second projection (Kelkar, Figure 4, and [0021] discloses that beveling the sharp corners of the cut outs 132a and 132b improves current conduction and prevents current congregation or sharp electric fields); and
wherein:
the first encapsulant covers the chamfers (Kelkar, Figure 8, shows the chamfered regions withing the dotted region of the encapsulant).
It would have been obvious tone one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Kelkar to bevel the sharp corners in the headframe of Jeon because Kelkar discloses that doing so improves the device by improving current conduction and preventing current congregation or sharp electric fields. Furthermore, it would have been obvious to have covered the chamfered regions with the encapsulant because doing so is taught by Kelkar and would provide support for the contacts.
The combination of Jeon and Kelkar fail to disclose the following limitations:
The electronic device of claim 13, further comprising:
grooves that extend partially into surfaces of the first projection and the second projection;
wherein:
the first encapsulant covers the grooves.
Loh discloses the following limitations:
grooves that extend partially into surfaces of the first projection and the second projection (Loh, Figure 10C, leak barriers 408, disclosed in [0110] as grooves that may be etched and/or stamped into the leadframe 400);
wherein:
the first encapsulant covers the grooves (Loh, Figure 11B shows the groves covered by package body 420 in Figure 11B).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Loh to the device of Jeon and to therefore have formed grooves in the electrodes and then covered the grooves with encapsulant. Doing so it taught by Loh to provide three-dimensional surface for bonding the package body and provide a longer path through which potential leaks would have to travel to get to the device.
Allowable Subject Matter
Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 16 would be allowable if written in independent form including all of the limitations of claim 11, because the closest prior art does not appear to disclose, alone or in combination, the limitations of an electronic device including an assembly board, a second modular package, a second substrate including two current carrying contacts and two control contacts, a third electronic contact coupled to the second substrate, a fourth component coupled to the second substrate, a second encapsulant covering the second substrate, third electronic component and fourth electronic component where the first and second external terminal are exposed from the second encapsulant, and the first and second modular package are coupled to the top of the assembly board. The closest prior art of record is Jeon, US 20250285931 A1. Jeon teaches a single electronic device in a package with leads matching those of one of the devices recited in claim 16. Jeon fails to disclose four devices and recited connections and placements withing the package. The other prior art of record fails to remedy this deficiency.
Claims 17 and 18 have been included because they depend from claim 16, directly or indirectly, and therefore incorporate all of the limitations of claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nagaraj et al., US 5336639 A, discloses semicircular notches 47, that serve as corner relief structures during the expansion and the contraction of the die attach region.
Milo et al., US 20210202365 A1, disclose the use of notches in leads that are at least partially covered by the mold.
Chi, US 20250006583 A1, discloses a device with two drain leads, separated by a gap, exposed on one side and thermistor, Kelvin source, gate, and sense leads exposed on the opposite side.
Sakai et al., US 20230253372 A1, discloses a device with two leads, separated by a gap, exposed on one side and seven leads exposed on the opposite side.
Fürgut at al., US 20250357232 A1, discloses a device with two leads, separated by a gap, exposed on one side and seven leads exposed on the opposite side.
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/LINDA J. FLECK/ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
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