DETAILED ACTION
Election/Restriction
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-15, drawn to an integrated circuit, classified in H10D1/714.
II. Claims 16-20, drawn to a method of integrated circuit, classified in H10D1/68.
The inventions are independent or distinct, each from the other because:
Inventions II and I are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the product as claimed can be made by another and materially different process such optical signal can change to electrical signal by switching transistor as opposed to photonic IC.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries);
(d) the prior art applicable to one invention would not likely be applicable to another invention;
(e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
During a telephone conversation with Charles Yeh on July 22, 2026 a provisional election was made without traverse to prosecute the invention of I, claims 1-15. Affirmation of this election must be made by applicant in replying to this Office action. Claims 16-20 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-10 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (Wang, US 2024/0079314 A1).
Regarding claim 1, Wang shows an integrated circuit comprising: a first capacitor (first capacitor 102 in FIG. 1 and [0044]) comprising a transistor (MOSCAP [0044]), wherein the transistor is positioned in a first layer (layer 112/113 in FIG. 1) of the integrated circuit (MOSCAP) and a second layer of the integrated circuit (MIMCAP [0044]), wherein the second layer (MCL1/MCL2 in FIG. 1) is positioned on the first layer, and wherein the transistor forms an anode ( anode 102a as shown in FIG. 13A and [0080]) and a cathode of the first capacitor ([0080]); and a second capacitor comprising (capacitor 104) a first set of metal fingers and a second set of metal fingers (see FIG. 13A), wherein the first set of metal fingers are interdigitated with the second set of metal fingers, wherein the first set of metal fingers and the second set of metal fingers are positioned in the second layer, wherein the first set of metal fingers are electrically connected to the cathode of the first capacitor, and wherein the second set of metal fingers are electrically connected to the anode of the first capacitor ([0080]).
Regarding claim 6, Wang shows an integrated circuit, wherein the cathode and the anode of the first capacitor ([0080]) are connected to a via ([0046]), wherein the via is arranged to transfer heat away from the cathode and the anode ([0080]).
Regarding claims 7-8, Wang shows an integrated circuit, wherein a photonic integrated circuit ([0047] capable of signal processing MOSCAP), wherein the integrated circuit is an electronic integrated circuit, and wherein the electronic integrated circuit is positioned on the photonic integrated circuit ( see capacitor 102 and 104 respectively).
Regarding claim 9, Wang shows an integrated circuit, further comprising a printed circuit board (element 106), wherein the integrated circuit (0044) is mounted directly on the printed circuit board (element 106).
Regarding claim 10, Wang shows an integrated circuit comprising: a first capacitor (first capacitor 102 in FIG. 1 and [0044]) comprising a transistor (MOSCAP [0044]), wherein the transistor is positioned in a first layer (layer 112/113 in FIG. 1) of the integrated circuit (MOSCAP) and a second layer of the integrated circuit (MIMCAP [0044]), wherein the second layer (MCL1/MCL2 in FIG. 1) is positioned on the first layer, and wherein the transistor forms an anode ( anode 102a as shown in FIG. 13A and [0080]) and a cathode of the first capacitor ([0080]); and a second capacitor comprising (capacitor 104) a first set of metal fingers and a second set of metal fingers (see FIG. 13A), wherein the first set of metal fingers are interdigitated with the second set of metal fingers, wherein the first set of metal fingers and the second set of metal fingers are positioned in the second layer, wherein the first set of metal fingers are electrically connected to the cathode of the first capacitor, and wherein the second set of metal fingers are electrically connected to the anode of the first capacitor ([0080]).
Regarding claim 15, Wang shows an integrated circuit, wherein the cathode and the anode of the first capacitor ([0080]) are connected to a via ([0046]), wherein the via is arranged to transfer heat away from the cathode and the anode ([0080]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang, US 2024/0079314 A1) in view of Cho ( US 2013/0093045 A1).
Regarding claims 2-5 and 11-14, Wang teaches the second capacitor (104 in FGI. 1) and anode and cathode [0080]), but fails to teaches a third set of metal fingers and a fourth set of metal fingers interdigitated with the third set of metal fingers, wherein the third set of metal fingers and the fourth set of metal fingers are positioned in a third layer of the integrated circuit, wherein the third layer is positioned on the second layer, and wherein the third set of metal fingers are electrically connected to the cathode of the first capacitor, and wherein the fourth set of metal fingers are electrically connected to the anode of the first capacitor and wherein a metal finger of the third set of metal fingers is positioned such that the metal finger of the third set of metal fingers crosses over metal fingers of the first set of metal fingers and metal fingers of the second set of metal fingers and further comprising a third capacitor comprising a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are positioned in a third layer of the integrated circuit different from the first layer and the second layer, and wherein the first metal layer is electrically connected to the cathode of the first capacitor, and wherein the second metal layer is connected to the anode of the first capacitor and wherein the third capacitor further comprises a dielectric positioned between the first metal layer and the second metal layer.
However Cho teaches a third set of metal fingers and a fourth set of metal fingers interdigitated with the third set of metal fingers, wherein the third set of metal fingers and the fourth set of metal fingers are positioned in a third layer of the integrated circuit, wherein the third layer is positioned on the second layer, and wherein the third set of metal fingers are electrically connected to the cathode of the first capacitor, and wherein the fourth set of metal fingers are electrically connected to the anode of the first capacitor and wherein a metal finger of the third set of metal fingers is positioned such that the metal finger of the third set of metal fingers crosses over metal fingers of the first set of metal fingers and metal fingers of the second set of metal fingers and further comprising a third capacitor comprising a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are positioned in a third layer of the integrated circuit different from the first layer and the second layer, and wherein the first metal layer is electrically connected to the cathode of the first capacitor, and wherein the second metal layer is connected to the anode of the first capacitor and wherein the third capacitor further comprises a dielectric positioned between the first metal layer and the second metal layer (see FIG. 12). At the time the invention was made, it would have been obvious to a person having ordinary skill in the art to add stack of metal finger teaching of Cho , because it would have able to stack capacitors vertically and capable of save space.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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/ELIAS ULLAH/ Primary Examiner, Art Unit 2893
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