DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/20/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 4-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hua (US 2024/0292606).
Regarding claim 1, Hua discloses, in at least figure, 7, 17, 21, and related text, a semiconductor structure, comprising:
a substrate (200, [46]) having a plurality of active regions (201/216, [88]) that are arrayed, wherein each of the plurality of active regions (201/216, [88]) comprises an active portion (201, [88]) and an active extension portion (216, [88]);
a word line gate structure (212/213/214 in 201, [83], [86], figures) positioned in the substrate (200, [46]), wherein the word line gate structure (212/213/214 in 201, [83], [86], figure) runs through the plurality of active regions (201/216, [88]), and the word line gate structure (212/213/214 in 201, [83], [86], figures) comprises a word line layer (213, [83]) and a word line isolation layer (214 in 201, [86]), and wherein the active extension portion (216, [88]) covers a surface of the active portion (201, [88]) and is at least partially positioned on the word line gate structure (212/213/214 in 201, [83], [86], figures); and
a word line isolation extension portion (214 in 216, [86]) positioned in the active extension portion (216, [88]), wherein the word line isolation extension portion (214 in 216, [86]) is connected to the word line isolation layer (214 in 201, [86]) and formed on a surface of the word line isolation layer (214 in 201, [86]).
Regarding claim 2, Hua discloses the semiconductor structure according to claim 1 as described above.
Hua further discloses, in at least figure, 7, 17, 21, and related text, an isolation region (215, [86]), wherein the isolation region (215, [86]) is formed between the plurality of active regions (201/216, [88]).
Regarding claim 4, Hua discloses the semiconductor structure according to claim 1 as described above.
Hua further discloses, in at least figure, 7, 17, 21, and related text, a capacitive contact portion (217, [95]), wherein the capacitive contact portion (217, [95]) is formed on the active extension portion (216, [88]) and is connected to the active extension portion (216, [88]).
Regarding claim 5, Hua discloses the semiconductor structure according to claim 1 as described above.
Hua further discloses, in at least figure, 7, 17, 21, and related text, a word line trench (trench for 212/213/214, figures) is formed in the substrate (200, [46]), the word line gate structure (212/213/214 in 201, [83], [86], figures) is formed in the word line trench (trench for 212/213/214, figures), and the word line gate structure (212/213/214 in 201, [83], [86], figures) further comprises a gate oxide layer (212, [60], [83]), wherein the gate oxide layer (212, [60], [83]) is formed on a side wall and a bottom wall of the word line trench (trench for 212/213/214, figures).
Regarding claim 6, Hua discloses the semiconductor structure according to claim 5 as described above.
Hua further discloses, in at least figure, 7, 17, 21, and related text, the word line layer (213, [83]) is formed on a side wall of the gate oxide layer (212, [60], [83]), and the word line isolation layer (214, [86]) is formed on a bottom wall of the gate oxide layer (212, [60], [83]), the side wall of the gate oxide layer (212, [60], [83]), and a side wall of the word line layer (213, [83]).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, and 3 that recite "the active extension portions are at least partially positioned on the surface of the isolation portion" in combination with other elements of the base claims 1, 2, and 3.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 5, and 7 that recite "the active extension portion is positioned on a surface of the gate oxide layer and a portion of the surface of the word line isolation layer" in combination with other elements of the base claims 1, 5, and 7.
Claims 8-14 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 8 that recite "forming an active extension layer on a surface of the substrate; removing a portion of the active extension layer to form an active extension portion, and forming a first opening exposing the word line isolation layer" in combination with other elements of the base claims 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811