Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 10-11, 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu (US 20230402438 A1).
Regarding claim 1, Liu discloses a semiconductor package (Fig. 2A), comprising:
a package substrate (206);
an interposer (108) disposed over (vertically “over”, See annotated figure for direction designation) the package substrate;
a stacked semiconductor device (the collection of chips 104) including a lower chip (one of 104, See annotated figure) and one or more upper chips (another of 104, See annotated figure), which are sequentially stacked over (vertically “stacked over”) the interposer;
a first semiconductor chip (102) stacked over (vertically “stacked over”) the interposer and spaced apart (horizontally “spaced apart”, See annotated figure for direction designation) from the stacked semiconductor device, and configured to interface with the lower chip ([0048]: “may distribute and route electrical signals between IC semiconductor devices (e.g., first semiconductor dies 102 and second semiconductor dies 104)”); and
one or more second semiconductor chips (204) disposed over the package substrate to interface with the lower chip ([0062]: “the one or more second semiconductor dies 104…separate circuits”).
Illustrated below is a marked and annotated figure of Liu: Fig. 2A.
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Regarding claim 2, Liu discloses the semiconductor package of claim 1 (Fig. 2A), wherein the lower chip includes:
a first interface circuit (connecting to some of 112) placed in a first area (whatever area corresponds to these 112, MPEP 2111) to interface with the first semiconductor chip through the interposer (previously cited in claim 1, repeated here: [0048]: “may distribute and route electrical signals between IC semiconductor devices (e.g., first semiconductor dies 102 and second semiconductor dies 104)”. Note: this citation describes signals in relation to the chips 104/102 and the interposer 108, thus, there must necessarily be some amount/kind of “first interface circuit”.); and
one or more second interface circuits (connecting to others of 112) that are placed in a second area (whatever area corresponds to these other 112, MPEP 2111) to interface with the one or more second semiconductor chips through the interposer and the package substrate (previously cited in claim 1, repeated here: [0062]: “the one or more second semiconductor dies 104…separate circuits”. Note: this citation describes signals in relation to the chip 104, the interposer 108 and the substrate 206, thus, there must necessarily be some amount/kind of “second interface circuits”.).
Regarding claim 3, Liu discloses the semiconductor package of claim 2, wherein the first area (cited in the claim 2 rejection as an area within lower chip 104) is disposed closer (horizontally “closer”) to the first semiconductor chip than the one or more second semiconductor chips (chip 104 is sandwiched horizontally between 1st chip 102 and 2nd chip 204, and is therefore “closer” within the scope of the claim), and wherein the second area (cited in the claim 2 rejection as another area within lower chip 104) is disposed closer to the one or more second semiconductor chips than the first semiconductor chip (chip 104 is sandwiched horizontally between 2nd chip 204 and 1st chip 102, and is therefore “closer” within the scope of the claim).
Regarding claim 10, Liu discloses the semiconductor package of claim 1 (Fig. 2A), further comprising: a printed circuit board (110) disposed over (vertically “over”) the package substrate, spaced apart (vertically “apart”) from the interposer, wherein the one or more second semiconductor chips are disposed over (horizontally “over”) the printed circuit board.
Regarding claim 11, Liu discloses the semiconductor package of claim 1 (Fig. 2A), wherein the stacked semiconductor device includes a high bandwidth memory (HBM) ([0045]: “HBM”), and the lower chip includes a base die of the HBM (Note: the cited die is vertically lower in the stack, and thus is “a base die” within the scope of the claim.).
Regarding claim 13, Liu discloses the semiconductor package of claim 1 (Fig. 2A), further comprising: a plurality of first micro-bumps (some of 112) disposed between (vertically “between”) the interposer and the lower chip and electrically connected to the first semiconductor chip through the interposer (previously cited in claim 1, repeated here: [0048]: “may distribute and route electrical signals between IC semiconductor devices (e.g., first semiconductor dies 102 and second semiconductor dies 104)”); and a plurality of second micro-bumps (others of 112) disposed between (vertically “between”) the interposer and the lower chip and electrically connected to the one or more second semiconductor chips through the interposer and the package substrate (previously cited in claim 1, repeated here: [0062]: “the one or more second semiconductor dies 104…separate circuits”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 3 above, and further in view of Lung (US 20210391303 A1).
Regarding claim 4, Liu discloses the semiconductor package of claim 3 (Fig. 2A), but fails to teach any specific configuration for “a third interface circuit”. Thus, Liu fails to teach the claimed configuration “wherein the lower chip further includes a third interface circuit placed between the first area and the second area to interface with the one or more upper chips through through-electrodes”.
Lung discloses wherein the lower chip (Fig. 3) further includes a third interface circuit (See annotated figure) placed between (horizontally “between” at least a portion) the first area (See annotated figure) and the second area (See annotated figure) to interface with the one or more upper chips through through-electrodes (236).
Modifying the lower chip configuration (of Liu) by incorporating the third interface circuit configuration (of Lung) would arrive at the claimed configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation chips (Liu: Fig. 2A: dies 104; Lung: Fig. 3: dies of S1) are vertically stacked as a memory module (Liu: [0045]: “die stacks…memory”; Lung: [0031]: “memory”). A person of ordinary skill in the art before the effective filing date would have been motivated to incorporate the third interface circuit configuration (of Lung) to enable functional operation of the chip stack otherwise disclosed (generically) by Liu. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed circuit configuration because it would enable functional operation of the chip stack otherwise disclosed by the prior art. MPEP 2143 (I)(C); MPEP 2144.04 (VI)(C).
Illustrated below is a marked and annotated figure of Fig. 3 of Lung.
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Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 13 above, and further in view of Lung.
Regarding claim 14, Liu discloses the semiconductor package of claim 13, but fails to teach which bumps are the first and second micro-bumps. Thus, Liu fails to teach “wherein a distance between the second micro-bumps and the first semiconductor chip is greater than that between the first micro-bumps and the first semiconductor chip, and wherein a distance between the first micro-bumps and the one or more second semiconductor chips is greater than that of the second micro-bumps and the one or more second semiconductor chips”.
Lung discloses wherein a distance between the second micro-bumps (Fig. 3: See annotated figure for designated bumps) and the first semiconductor chip (External Connections are cited here, See annotated figure. These connections correspond to the connections in Liu that pass through the interposer to the 2nd chip) is greater than that between the first micro-bumps and the first semiconductor chip (the designated 1st bumps are nearer the 1st chip than the designated 2nd bumps), and wherein a distance between the first micro-bumps and the one or more second semiconductor chips is greater than that of the second micro-bumps and the one or more second semiconductor chips (the designated 2nd bumps are nearer the External Connection than the designated 1st bumps).
Modifying the arrangement of the first and second micro-bumps (of Liu) by incorporating the arrangement disclosed by Lung would arrive at the claimed bump arrangement. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, the micro-bumps are connecting to a first chip (Liu: Fig. 2A: chip 102; Lung: Fig. 3: chip 140) and external circuitry (Liu: Fig. 2A: circuitry 116; Lung: Fig. 3: chip 122) through an interposer (Liu: Fig. 2A: interposer 108; Lung: Fig. 3: interposer 120). A person of ordinary skill in the art before the effective filing date would have been motivated to incorporate the bump arrangement (of Lung) to enable functional operation of the connections otherwise disclosed (generically) by Liu. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed bump arrangement because it would enable functional operation of the connections otherwise disclosed by the prior art. MPEP 2143 (I)(C); MPEP 2144.04 (VI)(C).
Allowable Subject Matter
Claims 5-7, 8-9, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 5-7 is the inclusion of the limitation “one or more sub-interface logics configured to transmit second signals for the one or more second semiconductor chips between the first semiconductor chip and the one or more second interface circuits” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “sub-interface logics”, “second semiconductor chips”, “between the first semiconductor chip and the one or more second interface circuits”, and the claimed relation “lower” in combination with all other limitations in claims 5, 4, 3, 2, and 1. The prior art of record teaches signal routing but does not provide sufficient specificity to teach, suggest, or render obvious the particularly claimed configuration. Searches elsewhere in the prior art did not find the specific signal routing configuration in relation to all the other requirements of the claim; and this configuration was not suggested by the prior are as an obvious variation when considering all other requirements of the claim.
The primary reason for the allowable subject matter of claim 8 is the inclusion of the limitation “wherein the lower chip further includes: an arbitrator configured to determine whether signals input from the first interface circuit correspond to the one or more upper chips or the one or more second semiconductor chips, and provide the input signals to the third interface circuit or one or more expanded controllers according to the determination result; and the one or more expanded controllers configured to generate signals corresponding to the one or more second semiconductor chips according to the input signals transmitted from the arbitrator, and transmit the generated signals to the second interface circuit” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “arbitrator” and “expanded controllers” in combination with all other limitations in claims 8, 4, 3, 2, and 1. The prior art of record is silent lacks this specific teaching. Searches elsewhere in the prior art did not find the specific functional circuitry in relation to all the other requirements of the claim; and this particular configuration was not suggested by the prior are as an obvious variation when considering all other requirements of the claim.
The primary reason for the allowable subject matter of claim 9 is the inclusion of the limitation “wherein the lower chip further includes one or more path controllers configured to determine whether signals input from the first interface circuit correspond to the one or more upper chips or the one or more second semiconductor chips, and provide the input signals to the second interface circuit or the third interface circuit according to the determination result” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “arbitrator” and “expanded controllers” in combination with all other limitations in claims 9, 4, 3, 2, and 1. The prior art of record is silent lacks this specific teaching. Searches elsewhere in the prior art did not find the specific functional circuitry in relation to all the other requirements of the claim; and this particular configuration was not suggested by the prior are as an obvious variation when considering all other requirements of the claim.
The primary reason for the allowable subject matter of claim 12 is the inclusion of the limitation “wherein the first semiconductor chip includes a memory controller, and the one or more second semiconductor chips include a low-power double data rate (LPDDR) type dynamic random access memory (DRAM)” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first semiconductor chip”, “memory controller”, “second semiconductor chips”, and “LPDDR” in combination with all other limitations in claims 12 and 1. Each of the respective chips and their functions were separately found in the prior art. However, these chips were not found within the context of the claimed arrangement; and searches elsewhere in the prior art do not suggest incorporating this particularly claimed functional configuration with, or as a modification of the prior art of record.
The primary reason for the allowable subject matter of claims 15-23 is the inclusion of the limitation “one or more sub-interface logics configured to transmit second signals for the one or more second semiconductor chips between the first semiconductor chip and the one or more second interface circuits” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “sub-interface logics”, “second semiconductor chips”, “between the first semiconductor chip and the one or more second interface circuits”, and the claimed relation “lower” in combination with all other limitations in claim 15. The prior art of record teaches signal routing but does not provide sufficient specificity to teach, suggest, or render obvious the particularly claimed configuration. Searches elsewhere in the prior art did not find the specific signal routing configuration in relation to all the other requirements of the claim; and this configuration was not suggested by the prior are as an obvious variation when considering all other requirements of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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