DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The prior art documents submitted by applicant in the Information Disclosure Statement filed on 05/21/24 and 5/29/25, have all been considered and made of record (note the attached copy of form PTO/SB/08a).
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 20200105705 A1).
With respect to claim 1, Cheng et al. (figures 1E-1G) disclose a semiconductor device, comprising an interconnect substrate (102) ([0014]); a photonic die (500, 600) ([0044]) over the interconnect substrate (102); and an underfill (UF1), disposed between the interconnect substrate (102) and the photonic die (500), wherein the photonic die (500, 600) comprises a first sidewall (left sidewall of 500) and a second sidewall (right sidewall of 500) opposite to the first sidewall, the first sidewall is covered by the underfill (UF1, figure 1F), and a central region of the second sidewall is free of the underfill (UF1) (see figure 1F).
With respect to claim 2, Cheng et al. (figures 1E-1G) disclose the semiconductor device, wherein an entirety of the second sidewall (right sidewall of 600) is free of the underfill (figure 1G).
With respect to claim 3, Cheng et al. (figures 1E-1G) disclose the semiconductor device, further comprising a dam structure (300) disposed between and overlapped with the photonic die (600) and the interconnect substrate (102).
With respect to claim 4, Cheng et al. (figures 1E-1G) disclose the semiconductor device,
wherein the photonic die (500) comprises a plurality of conductive connectors (200, 202, 204) bonded to the interconnect substrate (102), and the dam structure (300) is disposed between the conductive connectors (200, 202, 204) and the second sidewall of the photonic die (600).
With respect to claim 6, Cheng et al. (figures 1E-1G) disclose the semiconductor device, wherein the photonic die comprises a photonic coupler aligned with the central portion of the second sidewall [0015]).
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Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
9. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 7-16 are rejected under 35 U.S.C. 103(a) as being unpatentable over Cheng et al. (as cited above).
With respect to claim 7, Cheng et al. (figures 1E-1G) disclose a semiconductor device, comprising: an interconnect substrate (102) ([0014]); a photonic die (500, 600) ([0044]) over the interconnect substrate (102); and a dam structure (300) disposed between the interconnect substrate (102) and the photonic die (600), wherein the dam structure (300) extends along a first sidewall of the photonic die (600) (figure 1G).
Cheng et al. do not explicitly disclose the dam structure has a first length greater than 1/10 of a second length of the first sidewall.
However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Systems, Inc., 725 F. 2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cheng to form the dam structure having a first length greater than 1/10 of a second length of the first sidewall as claimed, because the dimensions can be varied depending upon the device in a particular application.
With respect to claim 8, Cheng et al. (figures 1E-1G and 4A) disclose the semiconductor device, wherein the first length (H300) of the dam structure (300) is substantially equal to the second length (H604) of the first sidewall.
With respect to claim 9, Cheng et al. (figures 1E-1G and 2) disclose the semiconductor device, wherein the dam structure (300) extends along a central portion of the first sidewall of the photonic die (figure 2).
With respect to claim 10, Cheng et al. (figures 1E-1G) disclose the semiconductor device, further comprising an underfill (UF1), wherein the underfill extends along a second sidewall opposite to the first sidewall, a third sidewall and a fourth sidewall of the photonic die (figure 1E and [0025]).
With respect to claim 11, Cheng et al. (figures 1E-1G) disclose the semiconductor device, wherein the underfill (UF1) further surrounds at least one of a corner between the third sidewall and the first sidewall and a corner between the third sidewall and the first sidewall ([0025], figures 1E-1F).
With respect to claim 12, Cheng et al. (figures 1E-1G) disclose the semiconductor device, wherein the underfill (UF1) further extends along the first sidewall without covering the dam structure (300, figure 1F).
With respect to claim 13, Cheng et al. (figures 1E-1G) disclose the semiconductor device, wherein a portion of the dam structure extends beyond the first sidewall ([0025]).
With respect to claim 14, Cheng et al. (figures 1E-1G) disclose the semiconductor device, wherein a material of the dam structure comprises an UV glue, a thermal adhesive, a solder resist, a metal or a combination thereof ([0018]).
With respect to claim 15, Cheng et al. (figures 1E-1G) disclose the semiconductor device,
wherein the dam structure comprises a stack of a first conductive layer, a second metal layer and a solder layer sandwiched between the first and second conductive layers ([0018]).
With respect to claim 16, Cheng et al. (figures 1E-1G) disclose the semiconductor device,
wherein the dam structure (300) has a shape of a partial sphere, a rectangle (figure 1E) or a trapezoid in a cross-sectional view.
Allowable Subject Matter
11. Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose the semiconductor device, wherein the second sidewall of the photonic die overhangs a sidewall of the interconnect substrate as recited in claim 5.
12. Claims 17-20 are allowed.
The prior art of record fails to disclose or reasonably suggest all the limitations of claim 17. Specifically, the prior art fails to disclose a method of forming a semiconductor device as set forth in claim 17.
Claims 18-20 depend from claim 17.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al. (US-10340249-B1) disclose a semiconductor device. Kim et al. (US-7572065-B2) disclose photonic semiconductor devices.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jennifer Doan whose telephone number is (571) 272-2346. The examiner can normally be reached on Monday to Friday from 7:00am to 3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached on 571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JENNIFER DOAN/Primary Examiner, Art Unit 2874
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