DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 7, 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated over Siemieniec et al. (US PGpub: 2021/0408279 A1), herein after Siemieniec.
Regarding claim 1, Siemieniec teaches a semiconductor device, in FIG. 6 and 7, comprising a semiconductor layer and a trench gate structure(150) , wherein the semiconductor layer has a first surface and a second surface opposite to each other, the trench gate structure is at least partially located in a trench on the first surface of the semiconductor layer,
the semiconductor layer comprises:
a source region (110), extending from the first surface toward the second surface;
a drift region (131) and a body region (120), wherein at least a part of the drift region is located between the body region and the second surface of the semiconductor layer (drift region is situated between body region (120) and second surface (102)), and the body region (indicated as "p") has a first part located between the source region and the drift region; and
a channel drain region, located between the first part of the body region and the drift region (n (137), situated below n+ and body region p (120)) and so that the source region, the first part of the body region and the channel drain region are sequentially adjoining in a direction of the first surface toward the second surface and adjoin a first sidewall of the trench gate structure (visible on the left side of the trench structure 150),
wherein the source region, the channel drain region, and the drift region are of a first conductivity type (indicated as n-type), the body region is of a second conductivity type (indicated as p-type), and the first conductivity type is opposite to the second conductivity type.
Claim 1 is also disclosed in Basler et al. (US: 20210159316 A1 (Fig.4): a gate trench structure (150), a drift region (131 ), a source region (110, n-doped), a body region (120, 160, p- doped) and a "channel drain region" (137).
Regarding claim 2, Siemieniec teaches the semiconductor device according to claim 1, wherein a doping concentration of the channel drain region is greater than a doping concentration of the drift region (Paragraph [0102]). Also, in Basler et al. see Paragraph [0036].
Regarding claim 3, Siemieniec teaches the semiconductor device according to claim 1, wherein the first part, a second part and a third part of the body region are sequentially adjoining along a width direction of the trench gate structure, the second part of the body region adjoins a second sidewall of the trench gate structure and the drift region, respectively, the third part of the body region extends from a bottom surface of the trench gate structure toward the second surface and adjoins the drift region, the channel drain region is separated from the third part of the body region by the drift region, the first sidewall is opposite to the second sidewall (FIG. 6 and 7, 3 parts of the body region indicated as p, p1 and p2. Even though there is no clear indication of the bottom border of the current spreading layer 137, Fig.6 shows a second part of the body reaching below the depth of the trench. In Fig.7, showing another embodiment, the second part of the body is not reaching to the bottom of the trench and a contact of the region 137 with the third body region is shown. In contrast, the embodiment in Fig.6 does not show such a contact. Therefore the embodiment in Fig.6 is interpreted as having no contact between the third body region and the current spreading region).
Regarding claim 4, Siemieniec teaches the semiconductor device according to claim 3, wherein the second part of the body region comprises a first sub-region and a second sub-region that are connected, the first sub-region adjoins the first part of the body region, the second sub-region adjoins the third part of the body region, wherein a distance from an edge of the channel drain region facing toward the second surface to the first surface is a first distance, a distance from an edge of the first sub-region facing toward the second surface to the first surface is a second distance, a distance from an edge of the second sub-region facing toward the second surface to the first surface is a third distance, the third distance is greater than the first distance, the first distance is greater than the second distance, so that the channel drain region is separated from the second sub-region by the drift region along the width direction of the trench gate structure (Fig.6, The region 161 which is considered as "second part of the body region", can be subdivided into two parts being vertically aligned on top of each other which leads to subregions having different depths as claimed.).
Regarding claim 6, Siemieniec teaches the semiconductor device according to claim 1, wherein a distance from an edge of the channel drain region facing toward the second surface to the first surface is a first distance, a distance from a bottom surface of the trench gate structure to the first surface is a fourth distance, the first distance is not greater than the fourth distance (Fig.7 depth of 137 smaller than the depth of 162).
Claim 6 is also disclosed in Basler et al. (US: 20210159316 A1 (Fig.4) in Fig.4, depth of 137 the same as 160.
Regarding claim 7, Siemieniec teaches the semiconductor device according to claim 1, wherein a distance from an edge of the channel drain region facing toward the second surface to the first surface is a first distance, a distance from a bottom surface of the trench gate structure to the first surface is a fourth distance, the first distance is greater than the fourth distance, and the channel drain region adjoins a part of the bottom surface of the trench gate structure (Fig.7, elements 137, 162).
Regarding claim 12, Siemieniec teaches the semiconductor device according to claim 1, wherein the semiconductor layer comprises a SiC semiconductor layer (Paragraphs [0003], [0033]).
Regarding claim 13, Siemieniec teaches the semiconductor device according to claim 1, wherein the semiconductor device is a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor (Paragraph [0108]).
Regarding claim 14, Siemieniec teaches the semiconductor device according to claim 3, wherein between two trench gate structures, the source region (110) extends from the first sidewall of one trench gate structure towards the second sidewall of the other trench gate structure, and adjoins the second part of the source region (110, See FIG. 5, where first part of 110 near first sidewall of first trench gate and second 110 is near the second sidewall of the other trench gate and adjoins them).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (US PGpub: 2021/0408279 A1), herein after Siemieniec, in view of Basler et al. (US PGpub: 20210159316 A1), herein after Basler.
Regarding claim 5, Siemieniec does not explicitly teach the semiconductor device according to claim 1, wherein edges of the second part and the third part of the body region facing toward the second surface are connected.
However, Basler teaches in FIG. 4, only two body regions are shown (elements 120, 160), but the region 160 can be further divided into a part below the trench and a part connecting this bottom part with the region 120, both of these regions being connected at the edge facing to the second surface.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Siemieniec’s semiconductor device with other teaching from Basler in order to reduce fluctuations in electrical characteristics of the transistor. The major role would be that of improved activity and selectivity, and increase in thermal stability of catalytic materials.
Claims 8-10 is rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (US PGpub: 2021/0408279 A1), herein after Siemieniec, in view of LEENDERTZ et al. (US PGpub: 2020/0219972 A1), herein after LEENDERTZ.
Regarding claim 8, Siemieniec does not explicitly teach the semiconductor device according to claim 3, wherein the semiconductor layer further comprises a body contact region extending from the first surface toward the second surface and adjoins the body region, wherein the body contact region is of the second conductivity type (body region p (120)).
However, LEENDERTZ teaches in FIG. 2A, 4C, the body region may include a heavily doped body contact region adjoining (e.g., directly adjoining) the first load electrode and the first vertical extension of the separation regions may be equal to a vertical extension of the body contact portion. A maximum dopant concentration in the body contact portion may be equal to a maximum dopant concentration in the separation regions. the body regions 120 may include heavily doped body contact portions 125 adjoining (e.g., directly adjoining) the first surface (Paragraphs [0045], [0076], [0077]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Siemieniec’s semiconductor device with other teaching from LEENDERTZ in order to improve short-circuit ruggedness..
Regarding claim 9, Siemieniec teaches the semiconductor device according to claim 8, wherein along an extension direction of the trench gate structure, a part of the body contact region adjoins the second sidewall, another part of the body contact region has a space from the second sidewall, and the part of the body contact region adjoining the second sidewall and the part of the body contact having the space from the second sidewall are arranged alternatively along the extension direction of the trench gate structure, or the body contact region is separated from the second surface by the body region (the alternating regions along the trench having different p-dopant concentrations. The related technical problem is how to better control the gate to source capacitance).
This problem is also disclosed in Pfirsch et al. (US: 20210359117 A1) in Paragraph [0039]. the vertical semiconductor power device may further include a barrier region of the first or second conductivity type arranged between the body region and the drift region. For example, the barrier region may be a barrier region of the first conductivity type arranged in a mesa region between the body region and a bottom the trench gate structure or partly below the trench gate structure. The barrier region of the first conductivity type and the body region may be vertically spaced. The barrier may allow for improving device robustness, for example. In addition or as an alternative, the barrier region may be a barrier region of the second conductivity type arranged in a mesa region between the body region and a bottom the trench gate structure. The barrier region of the second conductivity type and the body region may be vertically spaced or directly adjoin one another, for example. The barrier may allow for increasing the carrier concentration during on-state of the device, for example. For example, the body contact structure may further include a contact in a contact groove. The third body contact sub-region may directly adjoin a side surface part of the contact. The contact groove may extend into the semiconductor body from the first main surface. The third body contact region sub-region may also adjoin a bottom side of the contact groove, for example. The contact groove may allow for improving a contact surface area to both the body contact region and the source region, for example. Thus, an electric contact resistance may be lowered, for example.
Regarding claim 10, Siemieniec teaches (in view of LEENDERTZ) the semiconductor device according to claim 8, wherein the body contact region adjoins the source region, or the body contact region is separated from the source region by the body region (LEENDERTZ teaches in FIG. 2A, 4C, maximum dopant concentration in the body contact portion may be equal to a maximum dopant concentration in the separation regions. the body regions 120 may include heavily doped body contact portions 125 adjoining (e.g., directly adjoining) the first surface (Paragraphs [0045], [0076], [0077]).).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (US PGpub: 2021/0408279 A1), herein after Siemieniec, in view of KINOSHITA et al. (US PGpub: 2019/0140091 A1), herein after 20210159316 A1.
Regarding claim 11, Siemieniec does not explicitly teach the semiconductor device according to claim 1, wherein the trench gate structure comprises a gate dielectric layer and a gate conductor, the gate dielectric layer covers an inner surface of the trench and covers part of first surface adjacent to the trench, the trench extending from the first surface toward the second surface, a part of the gate conductor is in the trench, another part extends outside the trench and covers the gate dielectric layer, wherein the gate dielectric layer is located between the gate conductor and the semiconductor layer, so as to separate the gate conductor and the semiconductor layer.
However, KINOSHITA teaches in FIG. 4, only two body regions are shown (elements 120, 160), but the region 160 can be further divided into a part below the trench and a part connecting this bottom part with the region 120, both of these regions being connected at the edge facing to the second surface.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Siemieniec’s semiconductor device with other teaching from KINOSHITA in order to improve on-resistance in order to improve the device functionality..
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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