DETAILED ACTION
This action is responsive to the following communications: the Application filed May 21, 2024, and the Response to Election / Restriction filed April 17, 2026.
Claims 1-23 are pending. Claims 21-23 are withdrawn from consideration as being drawn to non-elected inventions without traverse. Claims 1 and 10 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 14-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Onuki et al. (US 2017/0271516).
Regarding independent claim 1, Onuki et al. teach a memory device (see e.g., FIG. 1A) comprising:
a plurality of memory cells (MC1_1-MC2_2), each memory cell including a cell transistor (M1_1) having a back gate (back gate of MC1_1) that is shared with a cell transistor of an adjacent memory cell (see MC1_1 and MC1_2) and connected to a back gate line (BGL_1), a forward gate (gate of M1_1) that is connected to a corresponding word line (WL_1), and a cell capacitor (Cs) that is connected to a first electrode of the cell transistor (see M1_1);
a sub-word line driver (12; and e.g., para. 0066: … the peripheral circuits 12 perform writing and reading of data voltage to and from …) configured to apply a word line driving voltage (see FIGS. 1A-1B) to a selected word line;
a back gate driver (13; and e.g., para. 0064: … circuit 13 has a function of supplying a back gate voltage …) configured to change a voltage level of a back gate voltage (FIG. 1B: BGL_1) applied to a back gate line corresponding to the selected word line from a first voltage level to a second voltage level during an active period in which the selected word line (FIG. 2B: WL_1) is enabled (see FIG. 1B along with FIG. 1A); and
a sense amplifier configured to sense data through bit lines (e.g., FIG. 1: BL_1-BL_2, and e.g., para. 0063-0064: The peripheral circuit 12 … In a period in which … and reading of data voltage to and from …; and para. 0125: … the read bit line can be used to read out a data voltage …) connected to second electrodes of the cell transistors of the plurality of memory cells (see e.g., FIGS. 1A-1B and accompanying disclosure).
Onuki’s data read through bit lines does not explicitly disclose a sense amplifier.
However, bit line data coupled to sense amplifier is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Onuki et al. (US 11,657,867), FIG. 4: 32 and 143, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize bit line sense amplifier to read out because these conventional technology are well established in the art of the memory devices.
Regarding claim 2, Onuki et al. teach the limitations of claim 1.
Onuki et al. further teach the active period includes a charge sharing period (see e.g., FIG. 1B: T4, i.e., BGL_1, high level), a sensing period (BL_1 active period for data read), and a restoring period (FIG. 1B: T5, i.e., BGL_1 back to low level), and wherein a voltage level of the back gate voltage is changed from the first voltage level to the second voltage level within the charge sharing period (see FIGS. 1A-1B).
Regarding claim 3, Onuki et al. teach the limitations of claim 2.
Onuki et al. further teach the voltage level of the back gate voltage is changed from the second voltage level to the first voltage level within the sensing period or the restoring period (see e.g., FIGS. 1A-1B, i.e., BGL_1 back to low level can be interpreted as a restoring period).
Regarding claim 4, Onuki et al. teach the limitations of claim 1.
Onuki et al. further teach the voltage level of the back gate voltage is changed from the second voltage level to the first voltage level within the active period or within a precharge period in which the selected word line is disabled, the precharge period after the active period (see e.g., FIGS. 1A-1B and accompanying disclosure).
Onuki et al. do not explicitly disclose a precharge period.
However, precharge period before or after active period in a memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize precharge before or after active period because these conventional technology are well established in the art of the memory devices.
Regarding claim 5, Onuki et al. teach the limitations of claim 1.
Onuki et al. further teach the active period includes an offset cancellation period, a charge sharing period (see e.g., FIG. 1B: T4, i.e., BGL_1, high level), a sensing period (BL_1 active period for data read), and a restoring period (FIG. 1B: T5, i.e., BGL_1 back to low level), and wherein the voltage level of the back gate voltage is changed from the first voltage level to the second voltage level within the offset cancellation period or the charge sharing period (see FIGS. 1A-1B).
Onuki et al. do not explicitly disclose an offset cancellation period in a data active period.
However, offset cancellation sensing scheme in a memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize offset cancellation sensing because these conventional technology are well established in the art of the memory devices.
Regarding claims 6 and 20, Onuki et al. teach the limitations of claims 1 and 10, respectively.
Onuki et al. further teach the plurality of memory cells include: a first memory cell including a first cell transistor connected to a first word line, a first bit line, and a first back gate line, the first memory cell further including a first cell capacitor connected between a first electrode of the first cell transistor and a ground; a second memory cell including a second cell transistor connected to a second word line adjacent to the first word line, the first bit line, and the first back gate line, the second memory cell further including a second cell capacitor connected between a first electrode of the second cell transistor and the ground; and a third memory cell including a third cell transistor connected to a third word line adjacent to the second word line, the first bit line, and a second back gate line, the third memory cell further including a third cell capacitor connected between a first electrode of the third cell transistor and the ground (see e.g., FIG. 1A to extend memory array).
Regarding claim 7, Onuki et al. teach the limitations of claim 6.
Onuki et al. further teach the first voltage level is higher than the second voltage level, and wherein during the active period in which the second word line is enabled, a voltage level of the back gate voltage applied to the first back gate line decreases from the first voltage level to the second voltage level (see e.g., FIGS. 1A-1B and accompanying disclosure).
Regarding claim 8, Onuki et al. teach the limitations of claim 7.
Onuki et al. further teach during the active period in which the second word line is enabled, a voltage level of a third word line driving voltage applied to the third word line decreases (see e.g., FIGS. 1A-1B extending to third word line in a matrix memory array).
Regarding claim 9, Onuki et al. teach the limitations of claim 1.
Onuki et al. further teach the cell transistor includes an n-type transistor, wherein the second voltage level is lower than the first voltage level, wherein during the active period, the voltage level of the word line driving voltage increases from a first driving voltage level to a third driving voltage level that is higher than a second driving voltage level for turning on the cell transistor, and wherein during the active period, the voltage level of the back gate voltage decreases from the first voltage level to the second voltage level (see e.g., FIG. 1A to extend memory array).
Regarding independent claim 10, Onuki et al. teach a memory device (see e.g., FIG. 1A: 10) comprising:
a cell array structure (11) including a plurality of word lines (WL_1-WL_2), a plurality of bit lines (BL_1-BL_2), a plurality of back gate lines (BGL_1-BGL_2), and a plurality of memory cells (MC1_1-MC2_2), each memory cell configured to share a back gate with an adjacent memory cell through a back gate line connected thereto (see FIG. 1A); and
a peripheral circuit structure (12 and 13) including a peripheral circuit configured to apply a word line driving voltage (see FIG. 1B: WL_1) to a selected word line among the plurality of word lines, configured to apply a back gate voltage (BGL_1) to a back gate line that is connected to memory cells connected to the selected word line, and configured to sense data (e.g., para. 0063-0064: … reading of data …; and para. 0125: … the read bit line can be used to read out a data voltage) through at least one selected bit line among the plurality of bit lines,
wherein the peripheral circuit is configured to change a voltage level of the back gate voltage from a first voltage level to a second voltage level within an active period in which the selected word line is enabled (see e.g., FIG. 1B along with FIG. 1A).
Onuki et al. do not explicitly disclose the peripheral circuit structure overlapping vertically with at least a portion of the cell array structure.
However, 3D memory structure overlapping memory array and peripheral circuit is a well-known technology for a type of memory structure for its purpose.
For support, of the above asserted facts, see for example, Onuki et al. (US 11,657,867), FIG. 2A, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize 3D memory structure because these conventional technology are well established in the art of the memory devices.
Regarding claim 14, Onuki et al. teach the limitations of claim 10.
Onuki et al. further teach the voltage level of the back gate voltage is changed from the second voltage level to the first voltage level within the active period or a second precharge period after the active period in which the selected word line is disabled (see e.g., FIG. 1B and accompanying disclosure).
Regarding claim 15, Onuki et al. teach the limitations of claim 10.
Onuki et al. further teach the peripheral circuit includes a single back gate driver that is connected to the plurality of back gate lines and that is configured to apply the back gate voltage to each of the plurality of back gate lines (see e.g., FIG. 1A).
Onuki et al. do not explicitly disclose a single driver.
However, a single driver driving several loading lines is a well-known technology for a type of memory driver circuity for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a single signal driver because these conventional technology are well established in the art of the memory devices.
Regarding claim 16, Onuki et al. teach the limitations of claim 10.
Onuki et al. further teach the plurality of back gate lines includes a first back gate line group including first back gate lines, and a second back gate line group including second back gate lines, and wherein the peripheral circuit includes a first back gate driver connected to each of the first back gate lines and a second back gate driver connected to each of the second back gate lines (see e.g., FIG. 1A).
Regarding claim 17, Onuki et al. teach the limitations of claim 10.
Onuki et al. further teach the peripheral circuit includes a plurality of back gate drivers connected respectively to each of the plurality of back gate lines (FIG. 1A).
Regarding claims 18-19, Onuki et al. teach the limitations of claim 10.
Onuki et al. further teach during the active period, a voltage level of the word line driving voltage that is applied to the selected word line decreases; and the second voltage level is lower than the first voltage level, wherein the voltage level of the word line driving voltage increases from a first driving voltage level to a third driving voltage level that is higher than a second driving voltage level during the active period, and wherein the voltage level of the back gate voltage decreases from the first voltage level to the second voltage level during the active period (see e.g., FIGS. 1A-1B and accompanying disclosure).
However, increasing and decreasing word line voltage during a active period is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize varied word line voltages because these conventional technology are well established in the art of the memory devices.
Further, claims 2-5, 7-9, 14 and 18-19 are claimed functions. The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Because Tseng’s apparatus is substantially identical to applicant’s claimed device, the claimed functions are presumed inherent. MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); MPEP 2112.01(I) (quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I).
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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