DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to perfect the priority claim, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on May 21, 2024; August 15, 2025; September 3, 2025; October 29, 2025; and March 19, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner except as otherwise indicated.
Specification
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor device having a trench gate structure".
5. Claim 15 is objected to because of the following informalities: clarity.
The limitation “along the extension direction” is unclear as to which direction the claim is being referred to (i.e. horizontally from the first to second trench gate or vertically from the first to second surface).
For examination purposes, the limitation “along the extension direction” has been interpreted to mean in the horizontal direction, going from the first to second trench gate.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 2 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the term “close” in claim 2 is a relative term which renders the claim indefinite. The term “close” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term "close" renders the claim indefinite because the term makes it impossible to define the metes and bounds of the limitation.
For examination purposes, the limitations "second part is close to a second sidewall" and "the third part and second part are close to the same gate structure" will be interpreted as being in contact..
Regarding claim 10, claim 10 recites the limitations "the first sub-region" in the second line of the claim and "the " in the . There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, “the first sub-region” and “the second sub-region” will be interpreted as “a first sub-region” and “a second sub-region”
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-10, 13-14, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shimizu et al (US 2018/0337275 A1, hereafter Shimizu).
Regarding claim 1, Shimizu discloses a semiconductor device (Fig. 1 100), comprising a semiconductor layer (Fig. 1 10) and a trench gate structure (Fig. 1 16+18), wherein the semiconductor layer (10) has a first surface (Fig. 1 P1) and a second surface (Fig. 1 P2) opposite each other, the trench
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[AltContent: textbox (For the record, modified figure (Fig. 1 of Shimizu) discloses the semiconductor device disclosed by Shimizu. Annotated (in dotted lines) are the second body part (B2) with first (S1) and second (S2) subregions, the third body part (B3), the channel drain region (CD) and the first (D1), second (D2), third (D3), fourth (D4), fifth (D5) and sixth (D6) distances as described by the claimed invention. Modified is the addition of the body contact (BC) of Leendertz in the upper region of the second body part (B2), as described further in the office action.)]gate structure (16+18) is at least partially located in a trench (Fig. 1 22) on the first surface (P1) of the semiconductor layer (10),
the semiconductor layer (10) comprises:
a source region (Fig. 1 30), extending (Fig. 1) from the first surface (P1) toward the second surface (P2);
a drift region (Fig. 1 26) and a body region (Fig. 1 28+32+34), wherein at least a part of the drift region (26) is located between the body region (28+32+34) and the second surface (P2) of the semiconductor layer (10), and the body region has a first part (Fig. 1 28), a second part (modified Fig. 1 B2) and a third part (modified Fig. 1 B3) being sequentially adjoining along a width direction (Fig. 1) of the trench gate structure (16+18),
wherein the first part of the body region (28) is located between the source region (30) and the drift region (26) along a direction of the first surface (P1) to the second surface (P2), the first part of the body region (28) and the source region (30) both adjoin a first sidewall of the trench gate structure (left wall of 16+18),
the third part of the body region (B3) is located (Fig. 1) between a bottom surface of the trench gate structure (bottom of 16+18) and the second surface (P2), and at least part of the bottom surface of the trench gate structure (bottom of 16+18) is separated from the third part of the body region (B3) by the drift region (Fig. 1 26x, a sub-region of drift region 26) along the direction of the first surface (P1) to the second surface (P2),
the source region (30) and the drift region (26) are of a first conductivity type (Fig. 1, 30 and 26 disclosed as n-type; [0035]), the body region is of a second conductivity type (Fig. 1, 28+32+34 disclosed as p-type; [0035]), and the first conductivity type (denoted as n-type) is opposite to the second conductivity type (denoted as p-type).
Regarding claim 2¸ Shimizu discloses the semiconductor device according to claim 1, wherein the first part (28) and the second part (B2) of the body region are located (Fig. 1) between two trench gate structures (16a+18a, 16b+18b), the first part (28) adjoins the first sidewall of the trench gate structure (left wall of 16b+18b), the second part (B2) is close to a second sidewall of the trench gate structure (right wall of 16b+18b), the first surface (P1) is opposite (Fig. 1) to the second surface (P2), the third part (B3) and the second part (B2) are close to the same trench gate structure (16b+18b),
wherein, the second part (B2) adjoins the second sidewall (right wall of 16b+18b); or the second part (B2) is separated (Fig. 1) from the second surface (P2) by the drift region (26).
Regarding claim 3¸ Shimizu discloses the semiconductor device according to claim 2, wherein the second part of the body region (B2) comprises a first sub-region (S1) and a second sub-region (S2) that are connected,
the first sub-region (S1) adjoins (modified Fig. 1) the first part of the body region (28), the second sub-region (S2) adjoins (modified Fig. 1) the third part of the body region (B3),
wherein, a distance from an edge of the first part of the body region (28) facing toward the second surface (P2) to the first surface (P1) is a first distance (modified Fig. 1 D1), a distance from an edge of the first sub-region (S2) facing toward the second surface (P2) to the first surface (P1) is a second distance (modified Fig. 1 D2), a distance from an edge of the second sub-region (S2) facing toward the second surface (P2) to the first surface (P1) is a third distance (modified Fig. 1 D3), the third distance (D3) is greater (modified Fig. 1) than the second distance (D2) (modified Fig. 1), and the second distance (D2) is greater (modified Fig. 1) than the first distance (D1).
Regarding claim 4¸ Shimizu discloses the semiconductor device according to claim 3, wherein a distance from the bottom surface of the trench gate structure (bottom of 16+18) to the first surface (P1) is a fourth distance (modified Fig. 1 D4), the second distance (D2) is not less (modified Fig. 1 than the fourth distance (D4).
Regarding claim 5¸ Shimizu discloses the semiconductor device according to claim 4, wherein along the direction of the second surface (P2) to the first surface (P1), a distance between the third part (B3) and the bottom surface of the trench gate structure (bottom of 16+18) which are separated by the drift region (26) is a fifth distance (modified Fig. 1 D5),
a sum of the fourth distance (D4) and the fifth distance (D5) is equal (modified Fig. 1) to the second distance (D2).
Regarding claim 6¸ Shimizu discloses the semiconductor device according to claim 1, wherein edges of the second part (B3) and the third part (B3) of the body region (28+32+34) facing toward the second surface (P2) are connected (modified Fig. 1, connected at bottom of 32).
Regarding claim 7¸ Shimizu discloses the semiconductor device according to claim 1, wherein the semiconductor layer (10) further comprises a channel drain region (modified Fig. 1 CD; applicant’s specifications only define the drain region by location and as being same conductivity type as source and drift regions), located between the first part of the body region (28) and the drift region (26), so that the source region (30), the first part of the body region (28) and the channel drain region (CD) are sequentially adjoining (modified Fig. 1; 30, 28, and CD are in contact) in a direction of the first surface (P1) to the second surface (P2) and adjoin first sidewall of the trench gate structure (left side of 16+18; 30, 28, and CD are in contact with sidewall),
the channel drain region (CD) adjoins the drift region (26), the first part (28) and the second part (B2) of the body region (28+32+34), respectively, and the channel drain region (CD) is separated from the third part of the body region (B3) by the drift region (26), wherein the channel drain region (CD) is of the first conductivity type (modified Fig. 1 CD disclosed as n-type; [0127]).
Regarding claim 8¸ Shimizu discloses the semiconductor device according to claim 7, wherein a doping concentration ([0128]) of the channel drain region (CD) is greater than a doping concentration ([0128]) of the drift region (26).
Regarding claim 9¸ Shimizu discloses the semiconductor device according to claim 7, wherein a distance from an edge of the channel drain region (CD) facing toward the second surface (P2) to the first surface (P1) (modified Fig. 1, equivalent to D6) is not greater than a distance from the bottom surface of the trench gate structure (bottom of 16+18) to the first surface (P1) (modified Fig. 1, equivalent to D3);
or the distance from the edge of the channel drain region (CD) facing toward the second surface (P2) to the first surface (P1) (modified Fig. 1, equivalent to D6) is greater than the distance from the bottom surface of the trench gate structure (bottom of 16+18) to the first surface (P1) (modified Fig. 1, equivalent to D3), and the channel drain region (CD) adjoins a part of the bottom surface of the trench gate structure (bottom of 16+18) (modified Fig. 1, CD is in contact with bottom of 16+18).
Note that the current claim requires that the distance from an edge of the channel drain region facing toward the second surface to the first surface is either not greater or greater than the distance from the bottom surface of the trench gate structure to the first surface. As the prior art discloses it being greater than, the alternative will not be deemed to be patentable distinguishable over the prior art.
Regarding claim 10¸ Shimizu discloses the semiconductor device according to claim 7, wherein a distance from an edge of a first sub-region (modified Fig. 1 S1) facing toward the second surface (P2) to the first surface (P1) is a second distance (modified Fig. 1 D2),
a distance from an edge of a second sub-region (modified Fig. 1 S2) facing toward the second surface (P2) to the first surface (P1) is a third distance (modified Fig. 1 D3),
a distance from an edge of the channel drain region (CD) facing toward the second surface (P2) to the first surface (P1) is a sixth distance (modified Fig. 1 D2), D6),
the sixth distance (D6) is greater (modified Fig. 1) than the second distance (D2), and the third distance (D3) is greater (modified Fig. 1) than the sixth distance (D6), so that the channel drain region (CD) and the second sub-region (S2) are separated by the drift region (26) along a width direction of the trench gate structure (16+18).
Regarding claim 13¸ Shimizu discloses the semiconductor device according to claim 1, wherein the semiconductor layer (10) comprises a SiC semiconductor layer ([0034]).
Regarding claim 14¸ Shimizu discloses the semiconductor device according to claim 1, wherein the semiconductor device (100) is a metal-oxide semiconductor field effect transistor ([0034]) or an insulated gate bipolar transistor.
Note that the current claim requires a metal-oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor. As the prior art discloses a MOSFET, the alternative will not be deemed to be patentable distinguishable over the prior art.
Regarding claim 16¸ Shimizu discloses the semiconductor device according to claim 2, wherein between two trench gate structures (16a+18a, 16b+18b), the source region (30) extends (Fig. 1) from the first sidewall of one trench gate structure (left wall of 16b+18b) towards the second sidewall of the other trench gate structure (right wall of 16a+18a), and adjoins (modified Fig. 1) the second part of the body region (B2).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
15. Claims 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu as applied to claim 1 above, and further in view of Leendertz et al (US 2020/0219972 A1, hereafter Leendertz).
Regarding claim 11¸ Shimizu discloses the semiconductor device according to claim 1.
Shimizu does not disclose the semiconductor layer further comprises a body contact region extending from the first surface toward the second surface, and the body contact region adjoins the body region,
the body contact region adjoins the source region, or is separated from the source region by the body region,
wherein the body contact region is of the second conductivity type.
Leendertz discloses a semiconductor layer (Fig. 4C 100) further comprises a body contact region (Fig. 4C 171) extending from the first surface (Fig. 4C 101) toward the second surface (Fig. 4B 102; [0065]), and the body contact region (171) adjoins the body region (Fig. 4C 120+172+173),
the body contact region (171) adjoins the source region (Fig. 4C 110), or is separated from the source region by the body region,
wherein the body contact region (171) is of the second conductivity type (Fig. 4C; body region 120+172+173 disclosed as p-type, same as body contact region 171).
Leendertz is analogous to Shimizu in the art of semiconductor devices with trench gates.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add the body contact region of Leendertz to the body region in the device of Shimizu (Shimizu modified Fig. 1 BC) to improve conductivity by forming ohmic contacts between the body region and the source metal layer.
Note that the current claim requires the body contact region adjoins the source region or separated from the source region by the body region. As the prior art discloses the body contact region adjoins the source region, the alternative will not be deemed to be patentable distinguishable over the prior art.
Regarding claim 15¸ Shimizu and Leendertz discloses the semiconductor device according to claim 11, wherein along an extension direction (Fig. 1 SECOND DIRECTION) of the trench gate structure (16+18), a part of the body contact region (left half of BC) adjoins the second sidewall (right wall of 16+18), another part of the body contact region (right half of BC) has a space from the second sidewall (right wall of 16+18) (right half of BC has “gap” filled by left half of BC), and the part of the body contact region (left half of BC) adjoining the second sidewall (right wall of 16+18) and the part of the body contact (right half of BC) having the space from the second sidewall (right wall of 16+18) (right half of BC has “gap” filled by left half of BC) are arranged alternatively (Shimizu modified Fig. 1) along the extension direction of the trench gate structure (16+18),
or the body contact region (BC) is separated from the second surface (P2) by the body region (28+32+34).
16. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu as applied to claim 1 above, and further in view of Kinoshita et al (US 2019/0140091 A1, hereafter Kinoshita).
Regarding claim 12¸ Shimizu discloses the semiconductor device according to claim 1, wherein the trench gate structure (16+18) comprises a gate dielectric layer (16) and a gate conductor (18),
the gate dielectric layer (16) covers an inner surface of the trench (22) (Shimizu Fig. 1, covers inner surface of 22), the trench (22) extending (Shimizu Fig. 1) from the first surface (P1) toward the second surface (P2),
a part of the gate conductor (18) is in the trench (22) (Shimizu Fig. 1),
wherein the gate dielectric layer (16) is located between the gate conductor (18) and the semiconductor layer (10), so as to separate (Shimizu Fig. 1) the gate conductor (18) and the semiconductor layer (10).
Shimizu does not disclose the gate dielectric layer covers part of first surface adjacent to the trench, and another part (of the gate conductor) extends outside the trench and covers the gate dielectric layer.
Kinoshita discloses the gate dielectric layer (Fig. 1 9) covers part of first surface (Fig. 1 surface parallel to top of 8) adjacent to the trench (Fig. 1 21), and another part (of the gate conductor (10)) extends outside (Fig. 1) the trench (21) and covers the gate dielectric layer (9).
Kinoshita is analogous to Shimizu in the art of semiconductor devices with trench gates.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the features of Kinoshita into the device of Shimizu to improve device performance by avoiding an increase in on-resistance while enhancing tolerance to short-circuit failure, as discussed by Kinoshita ([0006]).
Conclusion
17. The following art made of record and not relied upon is pertinent to applicant’s disclosure.
Siemieniec et al (US 2021/0408279 A1) discloses a semiconductor device with a trench gate structure
Basler et al (US 2021/0159316 A1) discloses a semiconductor device with a trench gate structure
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B SUN whose telephone number is (571)699-0231. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/MICHAEL B SUN/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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