Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 requires in part “…wherein the pre-heating unit comprises a first lamp that is different from the upper lamp (106; Figure 1; [0031]).”. The claim does not specify what the structural difference is between the pre-heating unit first lamp and the upper lamp (106; Figure 1; [0031]). Are different by independent control, spectra, circuitry?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 13, 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu; Chen-Ying et al. (US 20250118576 A1). Wu teaches a semiconductor processing apparatus (Figure 1), comprising: a support (119; Figure 1; [0030]) configured to support a wafer; a chamber (137+187; Figure 1; [0031]) comprising an upper dome (116; Figure 1,8; [0030]) that is above the support (119; Figure 1; [0030]) and a lower dome (187; Figure 1; [0033]) that is below the support (119; Figure 1; [0030]); a facility cover (156,148; Figure 1; [0029]) that at least partially surrounds the chamber (137+187; Figure 1; [0031]); a pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) that is below the support (119; Figure 1; [0030]) and is configured to heat the wafer; an upper lamp (106; Figure 1; [0031]) that is on the chamber (137+187; Figure 1; [0031]) and is configured to heat the wafer; a first process gas supply unit (129; Figure 1) configured to supply a first process gas to the chamber (137+187; Figure 1; [0031]); a second process gas supply unit (196; Figure 1) configured to supply a second process gas to the chamber (137+187; Figure 1; [0031]); a valve (183; Figure 1) that is between the second process gas supply unit (196; Figure 1) and the chamber (137+187; Figure 1; [0031]); a pump (197; Figure 1) that is connected to the chamber (137+187; Figure 1; [0031]) and is configured to discharge gas from the chamber (137+187; Figure 1; [0031]); and a control unit (1070; Figure 1; [0050]-[0051]) that is configured to execute instructions (Figure 13; [0090]-[0099]) stored in a non-transitory storage medium (1072; Figure 1; [0050]-[0051]), wherein the instructions (Figure 13; [0090]-[0099]) comprise controlling the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1), the upper lamp (106; Figure 1; [0031]), the first process gas supply unit (129; Figure 1), and the second process gas supply unit (196; Figure 1), wherein the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) comprises a first lamp that is different from the upper lamp (106; Figure 1; [0031]), as claimed by claim 1. The Examiner interprets the claimed “different” as Wu’s independent control of Wu’s heating sources (106,138) as discussed in [0102].
Wu further teaches:
The semiconductor processing apparatus (Figure 1) of claim 1, wherein the instructions (Figure 13; [0090]-[0099]) comprise controlling the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) to heat the wafer before a thin film (“..one or more layers...”; [0041],[0095]) growth process is performed, as claimed by claim 2. See step 1304, 1306, 1308; Figure 13
The semiconductor processing apparatus (Figure 1) of claim 1, wherein: the first process gas comprises at least one of SiH4, Si2H6, SiCl2H2, SiCl3H, and SiCl4, the second process gas comprises at least one of at least one of GeH4, Ge2H6, GeH2Cl2, GeCl4, and Ge2Cl6, as claimed by claim 3. Applicant’s claim requirement for process gas identity is a claim requirement of intended use in the pending apparatus claims. Further, it has been held that claim language that simply specifies an intended use or field of use for the invention generally will not limit the scope of a claim (Walter , 618 F.2d at 769, 205 USPQ at 409; MPEP 2106). Additionally, in apparatus claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim (In re Casey,152 USPQ 235 (CCPA 1967); In re Otto , 136 USPQ 458, 459 (CCPA 1963); MPEP2115).
The semiconductor processing apparatus (Figure 1) of claim 1, wherein the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) is below the chamber (137+187; Figure 1; [0031]), as claimed by claim 13
The semiconductor processing apparatus (Figure 1) of claim 1, further comprising a reflector (810; Figure 8) that is on the chamber (137+187; Figure 1; [0031]) and the upper lamp (106; Figure 1; [0031]) and that is configured to reflect light emitted from the upper lamp (106; Figure 1; [0031]), as claimed by claim 15
A semiconductor processing apparatus (Figure 1), comprising: a chamber (137+187; Figure 1; [0031]) that comprises a support (119; Figure 1; [0030]) that is configured to support a wafer; a pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) that is below the support (119; Figure 1; [0030]); an upper lamp (106; Figure 1; [0031]) that is above the support (119; Figure 1; [0030]); and a control unit (1070; Figure 1; [0050]-[0051]) that is configured to execute instructions (Figure 13; [0090]-[0099]) stored in a non-transitory storage medium (1072; Figure 1; [0050]-[0051]) to control the semiconductor processing apparatus (Figure 1) to perform operations comprising: depositing (1308; Figure 13) metal on the wafer; heating (1304; Figure 13; [0093]) the metal to form a metal-semiconductor ([0041]) compound layer on the wafer; and growing a thin film (“..one or more layers...”; [0041],[0095]) between the wafer and the metal-semiconductor ([0041]) compound layer, wherein growing the thin film (“..one or more layers...”; [0041],[0095]) comprises forming a first thin film (“..one or more layers...”; [0041],[0095]) and forming a second thin film (“..one or more layers...”; [0041],[0095]) on the first thin film (“..one or more layers...”; [0041],[0095]), wherein forming the first thin film (“..one or more layers...”; [0041],[0095]) comprises: supplying a first process gas to the chamber (137+187; Figure 1; [0031]); heating (1304; Figure 13; [0093]) the wafer using the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) below the wafer; and heating (1304; Figure 13; [0093]) the wafer using the upper lamp (106; Figure 1; [0031]) to grow the first thin film (“..one or more layers...”; [0041],[0095]), as claimed by claim 16
The semiconductor processing apparatus (Figure 1) of claim 16, wherein the first thin film (“..one or more layers...”; [0041],[0095]) comprises silicon (Si), and wherein the second thin film (“..one or more layers...”; [0041],[0095]) comprises germanium (SiGe), as claimed by claim 17
The semiconductor processing apparatus (Figure 1) of claim 16, wherein forming the second thin film (“..one or more layers...”; [0041],[0095]) comprises: supplying the first process gas and a second process gas to the chamber (137+187; Figure 1; [0031]); and heating (1304; Figure 13; [0093]) the wafer using the upper lamp (106; Figure 1; [0031]) to grow the second thin film (“..one or more layers...”; [0041],[0095]), as claimed by claim 18
The semiconductor processing apparatus (Figure 1) of claim 16, wherein: the wafer comprises a first region and a second region, the metal-semiconductor ([0041]) compound layer is on the first region and is not on the second region, and the first thin film (“..one or more layers...”; [0041],[0095]) and the second thin film (“..one or more layers...”; [0041],[0095]) are on the first region, as claimed by claim 19. The claim recites intended use claim requirements that are specific to the wafer’s composition and not part of the claimed structure for the pending apparatus claims.
A semiconductor processing apparatus (Figure 1), comprising: a support (119; Figure 1; [0030]) configured to support a wafer; a chamber (137+187; Figure 1; [0031]) comprising an upper dome (116; Figure 1,8; [0030]) that is above the support (119; Figure 1; [0030]) and a lower dome (187; Figure 1; [0033]) that is below the support (119; Figure 1; [0030]); a facility cover (156,148; Figure 1; [0029]) that at least partially surrounds the chamber (137+187; Figure 1; [0031]); a pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) that is below the support (119; Figure 1; [0030]) and is configured to heat the wafer; an upper lamp (106; Figure 1; [0031]) that is on the chamber (137+187; Figure 1; [0031]) and is configured to heat the wafer; a gas inlet (123,117; Figure 1) on a first side of the chamber (137+187; Figure 1; [0031]); a gas outlet (190, 1092; Figure 1) on a second side of the chamber (137+187; Figure 1; [0031]); a first process gas supply unit (129; Figure 1) that is connected to the gas inlet (123,117; Figure 1) and is configured to supply a first process gas to the chamber (137+187; Figure 1; [0031]); a second process gas supply unit (196; Figure 1) that is connected to the gas inlet (123,117; Figure 1) and is configured to supply a second process gas to the chamber (137+187; Figure 1; [0031]); a valve (183; Figure 1) that is between the second process gas supply unit (196; Figure 1) and the chamber (137+187; Figure 1; [0031]); a pump (197; Figure 1) that is connected to the gas outlet (190, 1092; Figure 1) and is configured to discharge gas from the chamber (137+187; Figure 1; [0031]); and a control unit (1070; Figure 1; [0050]-[0051]) that is configured to execute instructions (Figure 13; [0090]-[0099]) stored in a non-transitory storage medium (1072; Figure 1; [0050]-[0051]), wherein the instructions (Figure 13; [0090]-[0099]) comprise controlling the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1), the upper lamp (106; Figure 1; [0031]), the first process gas supply unit (129; Figure 1), and the second process gas supply unit (196; Figure 1), wherein the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) comprises a first lamp that is different from the upper lamp (106; Figure 1; [0031]), wherein the instructions (Figure 13; [0090]-[0099]) comprise controlling the pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) to heat the wafer before a thin film (“..one or more layers...”; [0041],[0095]) growth process is performed, and wherein the instructions (Figure 13; [0090]-[0099]) comprise controlling the upper lamp (106; Figure 1; [0031]) to heat the wafer when the thin film (“..one or more layers...”; [0041],[0095]) growth process is performed, as claimed by claim 20. The Examiner interprets the claimed “different” as Wu’s independent control of Wu’s heating sources (106,138) as discussed in [0102].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chen-Ying et al. (US 20250118576 A1) in view of Kitamura; Masahito et al. (US 20160086801 A1). Wu is discussed above. Wu further teaches:
The semiconductor processing apparatus (Figure 1) of claim 1, further comprising: a first supply line (first supply line between 196 and 183; Figure 1) that connects the second process gas supply unit (196; Figure 1) and the valve (183; Figure 1); a second supply line (121; Figure 1) that connects the valve (183; Figure 1) and the chamber (137+187; Figure 1; [0031]) – claim 4
Wu does not teach:
an exhaust line that connects the valve (183; Figure 1) and the pump (197; Figure 1) – claim 4
The semiconductor processing apparatus (Figure 1) of claim 4, wherein the instructions (Figure 13; [0090]-[0099]) further comprise controlling the valve (183; Figure 1) so that the first supply line (first supply line between 196 and 183; Figure 1) is connected to the second supply line (121; Figure 1) or the exhaust line, as claimed by claim 5
Kitamura also teaches a film forming apparatus (Figure 1) including controlled (280; va4,vb4,vc4; Figure 4) bypass valves (va4,vb4,vc4; Figure 1; [0064]-[0065]) from three distinct gas sources (220a-c; Figure 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Wu to add Kitamura’s bypass valves (va4,vb4,vc4; Figure 1; [0064]-[0065]).
Motivation for Wu to add Kitamura’s bypass valves (va4,vb4,vc4; Figure 1; [0064]-[0065]) is for “…a stable supply of the precursor gas into the process chamber 201 may be rapidly started or stopped through switching of the valves.” as taught by Kitamura ([0088]).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chen-Ying et al. (US 20250118576 A1) in view of Iwamoto; Kunihiko et al. (US 20060180082 A1). Wu is discussed above. Wu does not teach:
Wu’s semiconductor processing apparatus (Figure 1) of claim 1, wherein Wu’s instructions (Figure 13; [0090]-[0099]) further comprise controlling Wu’s valve (183; Figure 1) such that Wu’s first process gas is supplied to Wu’s chamber (137+187; Figure 1; [0031]) during a first time period and such that Wu’s first process gas and Wu’s second process gas are supplied to Wu’s chamber (137+187; Figure 1; [0031]) during a second time period that is subsequent to Wu’s first time period, as claimed by claim 6
Wu’s semiconductor processing apparatus (Figure 1) of claim 6, wherein Wu’s instructions (Figure 13; [0090]-[0099]) further comprise controlling Wu’s valve (183; Figure 1) such that during Wu’s first time period, Wu’s second process gas is not supplied to Wu’s chamber (137+187; Figure 1; [0031]), as claimed by claim 7
Iwamoto also teaches a wafer processing apparatus (Figure 4,5,7A,8-12) including pulsed gas delivery over common time intervals (time bracketted by vetical lines; Figure 12) and pulsed gas closure during other time periods (ammonia time period; Figure 12) under a controller (Figure 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Wu to optimize Wu’s process gas delivery as taught by Iwamoto.
Motivation for Wu to optimize Wu’s process gas delivery as taught by Iwamoto is for prefferred film formation as taught by Wu (“..one or more layers...”; [0041],[0095]).
Claims 8, 10, 11, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chen-Ying et al. (US 20250118576 A1) in view of Iwamoto; Kunihiko et al. (US 20060180082 A1). Wu is discussed above. Wu does not teach:
Wu’s semiconductor processing apparatus (Figure 1) of claim 1, wherein Wu’s instructions (Figure 13; [0090]-[0099]) further comprise controlling Wu’s pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) to heat Wu’s wafer from a first temperature to a second temperature and to heat Wu’s wafer until a first time point, and wherein Wu’s instructions (Figure 13; [0090]-[0099]) further comprise controlling Wu’s upper lamp (106; Figure 1; [0031]) to heat Wu’s wafer to a third temperature that is greater than Wu’s second temperature and to heat Wu’s wafer until a second time point after Wu’s first time point, as claimed by claim 8
Wu’s semiconductor processing apparatus (Figure 1) of claim 8, wherein Wu’s instructions (Figure 13; [0090]-[0099]) further comprise controlling Wu’s pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) to maintain Wu’s third temperature of Wu’s wafer after Wu’s upper lamp (106; Figure 1; [0031]) heats Wu’s wafer to Wu’s third temperature, as claimed by claim 10
Wu’s semiconductor processing apparatus (Figure 1) of claim 8, wherein Wu’s first process gas supply unit (129; Figure 1) is configured to supply Wu’s first process gas to Wu’s chamber (137+187; Figure 1; [0031]) at a constant flow rate, as claimed by claim 11
Wu’s semiconductor processing apparatus (Figure 1) of claim 1, wherein Wu’s instructions (Figure 13; [0090]-[0099]) further comprise controlling Wu’s pre-heating unit (138; Figure 1; [0031]-”lamps”-Applicant’s 130; Figure 1) and Wu’s upper lamp (106; Figure 1; [0031]) to operate alternately and repeatedly, as controlled by claim 14
Iwamoto is discussed above. Iwamoto further teaches a wafer heating temperatrure profile (Figure 12) alternately and repeatedly as well as constant, over pulse time periods, flow rates.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Wu to optimize Wu’s control unit (1070; Figure 1; [0050]-[0051]) as taught by Iwamoto.
Motivation for Wu to optimize Wu’s control unit (1070; Figure 1; [0050]-[0051]) as taught by Iwamoto is for prefferred film formation as taught by Wu (“..one or more layers...”; [0041],[0095]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chen-Ying et al. (US 20250118576 A1) and Iwamoto; Kunihiko et al. (US 20060180082 A1) in view of Carlson; David K. et al. (US 20220162756 A1). Wu and Iwamoto are discussed above. Wu and Iwamoto do not teach Wu’s semiconductor processing apparatus (Figure 1) of claim 8, wherein an operating time of Wu’s upper lamp (106; Figure 1; [0031]) in which Wu’s upper lamp (106; Figure 1; [0031]) heats Wu’s wafer to Wu’s third temperature is in a range of about 0.1 ms to about 5 ms, as claimed by claim 9.
Carlson also teaches a lamp heated wafer processing apparatus with ms time operation of the heating flash lamps. ([0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Wu to use Carlson’s flash lamp as taught by Carlson.
Motivation for Wu to use Carlson’s flash lamp as taught by Carlson is for RTP heating as taught by Carlson ([0041]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wu; Chen-Ying et al. (US 20250118576 A1) and Iwamoto; Kunihiko et al. (US 20060180082 A1) in view of Yamazaki, Shunpei (US 20020084261 A1). Wu and Iwamoto are discussed above. Wu and Iwamoto do not teach Wu’s semiconductor processing apparatus (Figure 1) of claim 8, wherein Wu’s upper lamp (106; Figure 1; [0031]) is a xenon arc lamp. Yamazaki also teaches a lamp heated wafer procesing apparatus with xenon lamps ([0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Wu to use Yamazaki’s xenon lamps.
Motivation for Wu to use Yamazaki’s xenon lamps is for alternate and equivalent means for IR heating as taught by Yamazaki ([0049]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wafer film processing using heating control include US 20230017768 A1; US 20090117714 A1-51; US 20130203269 A1; US 20250270734 A1; US 20250354291 A1; US 20250029850 A1
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/Rudy Zervigon/ Primary Examiner, Art Unit 1716
Prosecution Insights