DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1 and 7.
Pending: 1-8.
Withdrawn: 7-8.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 5/21/2024, 2/25/2025, 4/6/2026 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Election/Restrictions
Applicant’s election without traverse of invention I claim 1-6 in the reply filed on 7/13/2026 is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: METHOD FOR MANUFACTURING SEMICONDUCTOR SWITCHING DEVICE WITH SELF-ALIGNED ELECTRIC FIELD RELAXATION REGION.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Takaya et al., US Patent 10153345 B2.
Re: Independent Claim 1, Takaya discloses a semiconductor substrate (12, fig. 2) having a gate trench (54, fig. 3) in an upper surface thereof;
a gate electrode (40, fig. 8) disposed in the gate trench (54, fig. 3) and insulated from the semiconductor substrate (12, fig. 2) by a gate insulating film (38, fig. 8);
an n-type source region (22, fig. 10) in contact with the gate insulating film (38, fig. 8) at a side surface of the gate trench (54, fig. 3);
a p-type body region (26b, fig. 9) in contact with the gate insulating film (38, fig. 8) at the side surface of the gate trench (54, fig. 3) below the source region (22, fig. 10);
a p-type electric field relaxation region (32, fig. 4) in contact with the gate insulating film (38, fig. 8) at a bottom surface of the gate trench (54, fig. 3); and
an n-type drift region (28-28a, fig. 11) in contact with the gate insulating film (38, fig. 8) at the side surface of the gate trench (54, fig. 3) below the body region (26b, fig. 9) and in contact with a side surface and a bottom surface of the electric field relaxation region (32, fig. 4),
the method comprising: forming the source region (22, fig. 10) and the body region (26b, fig. 9) in the semiconductor substrate (12, fig. 2) having the drift region (28-28a, fig. 11);
forming a mask (56, fig. 4) having an opening (54, fig. 4) on the upper surface of the semiconductor substrate (12, fig. 2) having the drift region (28-28a, fig. 11);
after the forming of the mask (56, fig. 4), forming the electric field relaxation region (32, fig. 4) in the drift region (28-28a, fig. 11) by implanting (column 7, lines 53-55) a p-type impurity into the semiconductor substrate (12, fig. 2) through the opening (54, fig. 4);
after the forming of the electric field relaxation region (32, fig. 4), forming the gate trench (54, fig. 3) by etching the upper surface of the semiconductor substrate (12, fig. 2) within the opening (54, fig. 4) of the mask (56, fig. 4) so that the electric field relaxation region (32, fig. 4) remains below the gate trench (54, fig. 3); and
after the forming of the gate trench (54, fig. 3), forming the gate insulating film (38, fig. 8) and the gate electrode (40, fig. 8).
Re: Claim 2, Takaya disclose(s) all the limitations of claim 1 on which this claim depends. Takaya further discloses: wherein in the forming of the electric field relaxation region (32, fig. 4), the electric field relaxation region (32, fig. 4) is formed so that a width (32b, fig. 7) of the electric field relaxation region (32a, fig. 7) increases toward a bottom of the electric field relaxation region (32, fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Takaya et al., US Patent 10153345 B2; in view of Masuda et al., US PG pub. 20120228640 A1.
Re: Claim 3, Takaya discloses all the limitations of claim 2 on which this claim depends. Takaya is silent regarding: wherein in the forming of the gate trench (54, fig. 3), the gate trench (54, fig. 3) is formed so that a width of the gate trench (54, fig. 3) reduces toward a bottom of the gate trench (54, fig. 3).
Masuda teaches wherein forming of gate trench, the gate trench is formed so that a width of the gate trench reduces toward a bottom of the gate trench (as shown in figure 4-figure 7).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include narrower width since this can reduce in size compared to the same width bottom which is advantageous for finer design and higher integration.
Re: Claim 4, Takaya discloses all the limitations of claim 1 on which this claim depends. Takaya is silent regarding: etching the side surface of the gate trench (54, fig. 3), after the forming of the gate trench (54, fig. 3).
Masuda teaches etching the side surface of the gate trench after the forming of the gate trench (fig. 5-6).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include narrower width since this can reduce in size compared to the same width bottom which is advantageous for finer design and higher integration.
Re: Claim 5, Takaya discloses all the limitations of claim 1 on which this claim depends. Takaya further discloses: wherein the gate trench (54, fig. 3) is formed so that a width of the bottom surface of the gate trench (54, fig. 3) is smaller than the width of the electric field relaxation region (32, fig. 4).
Takaya is silent regarding: the forming of the gate trench (54, fig. 3), the gate trench (54, fig. 3) is formed so that the electric field relaxation region (32, fig. 4) is in contact with a corner portion defined between the bottom surface and the side surface of the gate trench (54, fig. 3).
Masuda teaches in the forming of the gate trench (6, fig. 7), the gate trench is formed so that the electric field relaxation region (7, fig. 7) is in contact with a corner portion defined between the bottom surface and the side surface of the gate trench (6, fig. 7).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the field relaxing region covering the corner of the trench since by having the field relaxing region cover the corner of the trench can relax/redistribute the electric field away from the vulnerable trench bottom gate oxide corner and into a robust p-n junction, improving blocking voltage capability and long term gate oxide reliability.
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Takaya et al., US Patent 10153345 B2; in view of Ohse et al., US PG pub. 20180204905 A1.
Re: Claim 6, Takaya discloses all the limitations of claim 1 on which this claim depends. Takaya further discloses: wherein the drift region (28-28a, fig. 11) includes a low concentration region (28, fig. 11) and a high concentration region (28a, fig. 11) that has an n-type impurity concentration higher than that of the low concentration region (28, fig. 11) and disposed above the low concentration region (28, fig. 11), and in the forming of the electric field relaxation region (32, fig. 4).
Takaya is silent regarding: the electric field relaxation region (32, fig. 4) is formed in the high concentration region (28a, fig. 11) such that a bottom end of the electric field relaxation region (32, fig. 4) is located within the high concentration region (28a, fig. 11).
Ohse teaches the electric field relaxation region (4, fig. 10) is formed in the high concentration region (5, fig. 10) such that a bottom end of the electric field relaxation region (4, fig. 10) is located within the high concentration region (5, fig. 10).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include field relaxation region form in the high concentration layer since this can reduce on resistance and control where breakdown happen.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Takaya et al., US PG pub. 20100224932 A1”) Discloses a semiconductor 100 has a P.sup.- body region and an N.sup.- drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P.sup.- body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P.sup.-- diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P.sup.- body region and the P diffusion region, is formed. The P.sup.-- diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P.sup.-- diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.
* (“Takaya US PG pub. 20120187478 A1”) discloses a semiconductor device capable of suppressing deterioration in characteristics even when an Avalanche phenomenon occurs in the semiconductor device. The semiconductor device includes a first conductive type drift region; a second conductive type body region disposed on a front surface side of the drift region; a gate trench penetrating the body region and extending to the drift region; a gate electrode disposed within the gate trench; an insulator disposed between the gate electrode and a wall surface of the gate trench; and a second conductive type diffusion region surrounding a bottom portion of the gate trench. An impurity concentration and dimension of the diffusion region are adjusted such that a breakdown is to occur at a p-n junction between the diffusion region and the drift region when an Avalanche phenomenon is occurring.
* (“Saito et al., US PG pub. 20170012121 A1”) discloses a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.
* (“Singh et al., US Patent 5719409 A”) discloses a silicon carbide (SIC) metal-insulator semiconductor field effect transistor having a u-shaped gate trench and an n-type SiC drift layer is provided. A p-type region is formed in the SiC drift layer and extends below the bottom of the u-shaped gate trench to prevent field crowding at the corner of the gate trench. A unit cell of a metal-insulator semiconductor transistor is provided having a bulk single crystal SiC substrate of n-type conductivity SiC, a first epitaxial layer of n-type SiC and a second epitaxial layer of p-type SiC. First and second trenches extend downward through the second epitaxial layer and into the first epitaxial layer with a region of n-type SiC between the trenches. An insulator layer is formed in the first trench with the upper surface of the insulator on the bottom of the trench below the second epitaxial layer. A region of p-type SiC is formed in the first epitaxial layer below the second trench. Gate and source contacts are formed in the first and second trenches respectively and a drain contact is formed on the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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