DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2003/0062888 to Magliocco et al. (Magliocco) in view of US 5,157,664 to Waite (Waite).
Regarding claim 1, Magliocco discloses a test device for performing an electrical test on devices formed on the test device comprising:
a plurality of input/output terminals configured to be electrically connected to the devices formed on
a comparative circuit configured to receive a plurality of test signals from a device under test formed on the wafer, and generate a plurality of test result signals, based on the plurality of test signals (Magliocco, e.g., Fig. 8, in a given test site 104 of tester 102, comparators 126; also see Fig. 1 and paragraphs 37-40, each PE channel 120 includes a PE driver 124 capable of coupling signals to a pin 108 of the DUT 106, a comparator 126 for comparing an output signal with an expected output signal, and an error logic circuit 128 for coupling results of the comparison to an error capture memory (not shown) in the test site controller; accordingly, in Fig. 8, the comparators 126 in a given test site 104 of tester 102 (e.g., the uppermost test site 104 in Fig. 8), taken alone or in combination, constitute a comparative circuit configured to receive a plurality of test signals from the corresponding DUT 106 formed on the substrate and generate a plurality of test result signals (e.g., comparison results) based on the plurality of test signals received by the comparator(s) 126 from the DUT 106); and
a memory configured to receive the plurality of test result signals and store related to the device under test, which are indicated by the plurality of test result signals (Magliocco, e.g., Figs. 1 and 8 and paragraphs 37-40, an error logic circuit 128 for coupling results of the comparison to an error capture memory (not shown) in the test site controller 112).
Magliocco discloses that the DUT 106 can be one of a number of devices on a substrate and can be coupled to test system 100 via probes (see, e.g., paragraph 36), but Magliocco is not relied upon as explicitly stating that the substrate is a wafer. Magliocco nonetheless discloses that it is desirable to test the devices at several points during the manufacturing process including while they are still part of a wafer or substrate (Magliocco, e.g., paragraph 3). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Magliocco such that the DUTs 106 are tested while they are still a part of a wafer (e.g., with Magliocco’s substrate being a wafer) at least in view of Magliocco’s teaching that testing DUTs at this stage of the manufacturing process is advantageous.
Magliocco discloses that the DUT’s 106 may be may be memory arrays (see, e.g., paragraph 36), but Magliocco is not relied upon as explicitly disclosing that the stored error information includes bad cell information and repair information related to the device under test, which are indicated by the plurality of test result signals. Waite relates to test equipment for semiconductor memory devices and, more particularly, to a system which identifies a replacement scheme for removing defects in a memory device. Waite discloses in connection with Fig. 3 a tester subsystem 16 that writes a test pattern to each memory cell in the device under test, reads data stored in the device under test and compares data read from the device under test with the test pattern written to the device cells to identify defective cells, and an analysis subsystem 20 that analyzes the stored data to develop a repair scheme whereby one or more defective column or row lines are designated for replacement with redundant lines (Waite, e.g., col. 5, lines 29-44). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Magliocco in a case where the DUT 106 is a memory array such that that the stored error information includes bad cell information and repair information. In this way, in the manner disclosed by Waite, a repair scheme whereby one or more defective column or row lines are designated for replacement with redundant lines can be provided.
Regarding the language wherein the total number of the plurality of test signals received from the device under test at one time is an integer, the examiner first notes that the number of test signals received from a device under test at one time would appear to be entirely dependent on the type of device being tested. In this regard, with reference to Figs. 8 and 1 of Magliocco, the examiner notes that a given test site 104 can include a plurality of channels 120 (as indicated by “…” in Fig. 8 between channels 120 in each test site 104), and that the exact number of channels used to transmit/receive signals from a DUT 106 will be determined by the type of DUT 106 being tested, rather than by the structure of the test site 104 or its associated tester 102. The examiner further notes that in claim 1 the wafer and devices formed on the wafer are not affirmatively recited as elements of the claimed test device, but rather as structures with which the claimed test device is intended to be used/operated. Because the total number of the plurality of test signals received from the device under test would appear to be entirely dependent on the type of device under test, the claim language “wherein the total number of the plurality of test signals received from the device under test at one time is an integer” is considered to relate merely to a manner in which the claimed test device is used (e.g., the particular type of DUT to be tested) and is not understood to specify any additional structural/functional limitations of the claimed test device itself. The claim language “wherein the total number of the plurality of test signals received from the device under test at one time is an integer” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals corresponding to the 18 pads/pins of the DUT 106.
Claim 2 recites wherein the total number of the plurality of test signals corresponds to an integer of non-power-of-two. For reasons analogous to those discussed above in connection with claim 1, this language merely relates to a manner in which the claimed test device is used (e.g., the particular type of DUT tested) and is not interpreted as setting forth any further structural/functional limitations of the claimed test device itself. The claim language “wherein the total number of the plurality of test signals corresponds to an integer of non-power-of-two” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). Claim 2 is therefore rejected under 35 U.S.C. 103 as unpatentable over Magliocco in view of Waite for the reasons discussed above in connection with claim 1. The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals corresponding to the 18 pads/pins of the DUT 106, with 18 being a non-power-of-two.
Claim 3 recites wherein the total number of the plurality of test result signals generated at one time is an integer other than a power of two. For reasons analogous to those discussed above in connection with claim 1, this language merely relates to a manner in which the claimed test device is used (e.g., the particular type of DUT tested) and is not interpreted as setting forth any further structural/functional limitations of the claimed test device itself. The claim language “wherein the total number of the plurality of test result signals generated at one time is an integer other than a power of two” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). Claim 3 is therefore rejected under 35 U.S.C. 103 as unpatentable over Magliocco in view of Waite for the reasons discussed above in connection with claim 1. The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals (and therefore 18 test result signals) corresponding to the 18 pads/pins of the DUT 106, with 18 being an integer other than a power of two.
Regarding claim 4, Magliocco in view of Waite discloses wherein the plurality of test signals are each input through an independent input/output terminal from among the plurality of input/output terminals (see Magliocco in view of Waite as applied to claim 1, e.g., Magliocco, Fig. 8, noting that each channel 120 corresponds to an input/output terminal independent of the other channels 120).
Claim 5 recites wherein, among the plurality of input/output terminals, the total number of input/output terminals electrically connected to the device under test is an integer other than a power of two. For reasons analogous to those discussed above in connection with claim 1, this language merely relates to a manner in which the claimed test device is used (e.g., the particular type of DUT tested) and is not interpreted as setting forth any further structural/functional limitations of the claimed test device itself. The claim language “wherein, among the plurality of input/output terminals, the total number of input/output terminals electrically connected to the device under test is an integer other than a power of two” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). Claim 5 is therefore rejected under 35 U.S.C. 103 as unpatentable over Magliocco in view of Waite for the reasons discussed above in connection with claim 1. The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of input/output terminals electrically connected to the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 input/output terminals connected to the 18 pads/pins of the DUT 106, with 18 being an integer other than a power of two.
Regarding claim 6, Magliocco in view of Waite discloses wherein the plurality of input/output terminals are electrically connected to a plurality of data input/output pads of the devices formed on the wafer (see Magliocco in view of Waite as applied to claim 1, e.g., Magliocco, paragraph 36, DUT 106 can be coupled to test system 100 via a number of pins 108 or via probes (not shown) or contacting pads (not shown) on the substrate; also note in modified Magliocco DUTs 106 are tested while they are still a part of a wafer).
Claim 7 recites wherein, when a number of devices formed on the wafer is more than a first reference value but less than a second reference value, the total number of input/output terminals electrically connected to the device under test is N, wherein N is an integer of 2 or greater, and when the number of devices formed on the wafer is more than the second reference value but less than a third reference value, the total number of input/output terminals electrically connected to the device under test is N−1. For reasons analogous to those discussed above in connection with claim 1, this language merely relates to a manner in which the claimed test device is used (e.g., the particular type of DUT tested) and is not interpreted as setting forth any further structural/functional limitations of the claimed test device itself. The claim language “wherein, when a number of devices formed on the wafer is more than a first reference value but less than a second reference value, the total number of input/output terminals electrically connected to the device under test is N, wherein N is an integer of 2 or greater, and when the number of devices formed on the wafer is more than the second reference value but less than a third reference value, the total number of input/output terminals electrically connected to the device under test is N−1” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). Claim 7 is therefore rejected under 35 U.S.C. 103 as unpatentable over Magliocco in view of Waite for the reasons discussed above in connection with claim 1. The lack of patentable weight notwithstanding, the examiner notes in modified Magliocco’s arrangement of Fig. 8 that a number of devices 106 formed on the wafer is more than a first reference value (e.g., 1) but less than a second reference value (e.g., 5) and the total number of input/output terminals corresponding to channels 120 electrically connected to the device under test (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) is N, wherein N is an integer of 2 or greater.
Regarding claim 8, Magliocco in view of Waite discloses wherein the test device is configured to perform the electrical test on the devices formed on the wafer, in parallel (see Magliocco in view of Waite as applied to claim 1, e.g., Magliocco, Fig. 8, test system 100 including tester 102 is configured to perform the electrical test on DUTs 106 in parallel, see Magliocco, Abstract).
Regarding claim 10, Magliocco in view of Waite discloses wherein the test device is configured to generate the bad cell information related to the device under test, based on the plurality of test result signals received by the memory, and the test device further comprises a control circuit configured to generate the repair information corresponding to the bad cell information (see Magliocco in view of Waite as applied to claim 1, e.g., Waite, e.g., col. 5, lines 29-44).
Regarding claim 11, Magliocco in view of Waite discloses wherein the bad cell information related to the device under test comprises bad cell addresses of the device under test, included in the plurality of test result signals, and the repair information comprises repair cell addresses respectively corresponding to the bad cell addresses (see Magliocco in view of Waite as applied to claim 10, e.g., Waite, e.g., col. 5, lines 29-44).
Claim 12 recites an operating method of a test device for performing an electrical test on devices formed on a substrate, the operating method comprising:
receiving a plurality of test signals from a device under test formed on the wafer;
generating a plurality of test result signals, based on results of comparing the received plurality of test signals with a test reference voltage;
storing bad cell information related to the device under test in a memory of the test device, based on the plurality of test result signals; and
generating repair information corresponding to the bad cell information,
wherein the total number of the plurality of test signals received from the device under test at one time is an integer,
and is rejected under 35 U.S.C. 103 as unpatentable over Magliocco in view of Waite for reasons analogous to those discussed above in connection with the rejection of claim 1, noting in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals corresponding to the 18 pads/pins of the DUT 106.
Regarding claim 13, Magliocco in view of Waite discloses wherein the total number of the plurality of test signals corresponds to an integer of non-power-of-two (see Magliocco in view of Waite as applied to claim 12, noting in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals corresponding to the 18 pads/pins of the DUT 106, with 18 being an integer of non-power-of-two).
Regarding claim 14, Magliocco in view of Waite discloses wherein the total number of the plurality of test result signals generated at one time is an integer other than a power of two (see Magliocco in view of Waite as applied to claim 12, noting in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals (and therefore 18 test result signals) corresponding to the 18 pads/pins of the DUT 106, with 18 being an integer other than a power of two).
Regarding claim 15, Magliocco discloses a test system for performing an electrical test on devices formed on the test system comprising:
including a plurality of input/output pins configured to be electrically connected to the devices formed on includes a PE driver 124 capable of coupling signals to a pin 108 of the DUT 106; also see, e.g., paragraph 36, by DUT 106 it is meant any electronic component, module, or integrated circuit (IC) having logic circuits, memory arrays, analog circuits or any combination thereof; DUT 106 can be a die, packaged or can be one of a number of devices on a substrate (not shown); DUT 106 can be coupled to test system 100 via a number of pins 108 or via probes (not shown) or contacting pads (not shown) on the substrate; also see, e.g., Fig. 3 and paragraph 47, by material handler it is meant any suitable material handler having means for holding and electrically coupling the DUT 106 with the test system 100 including, for example, probers, strip or panel handlers, and vertical plane or gravity feed handlers); and
a test device configured to test a device under test formed on
wherein probes are configured to receive a plurality of test signals through the plurality of input/output pins from the device under test, and provide the received plurality of test signals to the test device (see Magliocco as applied above, in a case where probes are used to connected to the DUTs 106 in Fig. 8, the probes are configured to receive a plurality of test signals through the plurality of input/output pins or the probe from the DUT 106, and provide the received plurality of test signals to the tester 102),
wherein the test device comprises:
a plurality of input/output terminals configured to receive the plurality of test signals from
a comparative circuit configured to generate a plurality of test result signals, based on the plurality of test signals (Magliocco, e.g., Fig. 8, in a given test site 104 of tester 102, comparators 126; also see Fig. 1 and paragraphs 37-40, each PE channel 120 includes a PE driver 124 capable of coupling signals to a pin 108 of the DUT 106, a comparator 126 for comparing an output signal with an expected output signal, and an error logic circuit 128 for coupling results of the comparison to an error capture memory (not shown) in the test site controller; accordingly, in Fig. 8, the comparators 126 in a given test site 104 of tester 102 (e.g., the uppermost test site 104 in Fig. 8), taken alone or in combination, constitute a comparative circuit configured to receive a plurality of test signals from the corresponding DUT 106 formed on the substrate and generate a plurality of test result signals (e.g., comparison results) based on the plurality of test signals received by the comparator(s) 126 from the DUT 106); and
a memory configured to receive the plurality of test result signals and store related to the device under test, which are indicated by the plurality of test result signals (Magliocco, e.g., Figs. 1 and 8 and paragraphs 37-40, an error logic circuit 128 for coupling results of the comparison to an error capture memory (not shown) in the test site controller).
Regarding the language wherein the total number of input and output pins from among the plurality of input/output pins electrically connected to the device under test is an integer, the examiner first notes that the number of test signals received from a device under test at one time would appear to be entirely dependent on the type of device being tested. In this regard, with reference to Figs. 8 and 1 of Magliocco, the examiner notes that a given test site 104 can include a plurality of channels 120 (as indicated by “…” in Fig. 8 between channels 120 in each test site 104), and that the exact number of channels used to transmit/receive signals from a DUT 106 will be determined by the type of DUT 106 being tested, rather than by the structure of the test site 104 or its associated tester 102. The examiner further notes that in claim 15 the wafer and devices formed on the wafer are not affirmatively recited as elements of the claimed test system, but rather as structures with which the claimed test system is intended to be used/operated. Because the total number of the plurality of test signals received from the device under test (and, therefore, the number of input/output probes) would appear to be entirely dependent on the type of device under test, the claim language “wherein the total number of input and output pins from among the plurality of input/output pins electrically connected to the device under test is an integer” is considered to relate merely to a manner in which the claimed test system is used (e.g., the particular type of DUT to be tested) and is not understood to specify any additional structural/functional limitations of the claimed test system itself. The claim language “wherein the total number of input and output pins from among the plurality of input/output pins electrically connected to the device under test is an integer” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8), and therefore the number of input/ouput probes, is an integer, i.e., 18 input/output probes corresponding to the 18 pads/pins of the DUT 106.
Magliocco is not relied upon as explicitly disclosing that the probes (see, e.g., paragraph 36) are implemented using a probe card. The examiner takes Official notice of the fact that implementing probes for DUT testing using a probe card was well-known and conventional before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Magliocco such that the probes are implemented using a probe card in view of the well-known and conventional use of probe cards for providing a test interface for DUT testing.
Magliocco discloses that the DUT 106 can be one of a number of devices on a substrate and can be coupled to test system 100 via probes (see, e.g., paragraph 36), but Magliocco is not relied upon as explicitly stating that the substrate is a wafer. Magliocco nonetheless discloses that it is desirable to test the devices at several points during the manufacturing process including while they are still part of a wafer or substrate (Magliocco, e.g., paragraph 3). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Magliocco such that the DUTs 106 are tested while they are still a part of a wafer at least in view of Magliocco’s teaching that testing DUTs at this stage of the manufacturing process is advantageous.
Magliocco discloses that the DUT’s 106 may be may be memory arrays (see, e.g., paragraph 36), but Magliocco is not relied upon as explicitly disclosing that the stored error information includes bad cell information and repair information related to the device under test, which are indicated by the plurality of test result signals. Waite relates to test equipment for semiconductor memory devices and, more particularly, to a system which identifies a replacement scheme for removing defects in a memory device. Waite discloses in connection with Fig. 3 a tester subsystem 16 that writes a test pattern to each memory cell in the device under test, reads data stored in the device under test and compares data read from the device under test with the test pattern written to the device cells to identify defective cells, and an analysis subsystem 20 that analyzes the stored data to develop a repair scheme whereby one or more defective column or row lines are designated for replacement with redundant lines (Waite, e.g., col. 5, lines 29-44). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Magliocco in a case where the DUT 106 is a memory arrays such that that the stored error information includes bad cell information and repair information. In this way, in the manner disclosed by Waite, a repair scheme whereby one or more defective column or row lines are designated for replacement with redundant lines can be provided.
Claim 16 recites wherein the total number of the plurality of test signals received from the device under test at one time is an integer other than a power of two. For reasons analogous to those discussed above in connection with claim 15, this language merely relates to a manner in which the claimed test system is used (e.g., the particular type of DUT tested) and is not interpreted as setting forth any further structural/functional limitations of the claimed test system itself. The claim language “wherein the total number of the plurality of test signals received from the device under test at one time is an integer other than a power of two” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). Claim 16 is therefore rejected under 35 U.S.C. 103 as unpatentable over Magliocco in view of Waite for the reasons discussed above in connection with claim 15. The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals corresponding to the 18 pads/pins of the DUT 106, with 18 being an integer other than a power of two.
Claim 17 recites wherein the total number of the plurality of test result signals generated at one time is an integer other than a power of two. For reasons analogous to those discussed above in connection with claim 15, this language merely relates to a manner in which the claimed test system is used (e.g., the particular type of DUT tested) and is not interpreted as setting forth any further structural/functional limitations of the claimed test system itself. The claim language “wherein the total number of the plurality of test result signals generated at one time is an integer other than a power of two” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). Claim 17 is therefore rejected under 35 U.S.C. 103 as unpatentable over Magliocco in view of Waite for the reasons discussed above in connection with claim 15. The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals (and therefore 18 test result signals) corresponding to the 18 pads/pins of the DUT 106, with 18 being an integer other than a power of two.
Regarding claim 18, Magliocco in view of Waite discloses wherein the plurality of test signals are each input through an independent input/output pin, and among the plurality of input/output pins (see Magliocco in view of Waite as applied to claim 15, e.g., Magliocco, Fig. 8, noting that each channel 120 corresponds to an input/output terminal independent of the other channels 120; in modified Magliocco each of the test signals will therefore be input through an independent input/output pin of the probe card).
Claim 18 further recites the number of input/output pins electrically connected to the device under test is an integer other than a power of two. For reasons analogous to those discussed above in connection with claim 15, this language merely relates to a manner in which the claimed test system is used (e.g., the particular type of DUT tested) and is not interpreted as setting forth any further structural/functional limitations of the claimed test system itself. The claim language “the number of input/output pins electrically connected to the device under test is an integer other than a power of two” therefore carries no patentable weight. See, e.g., MPEP 2114.II (manner of operating the device does not differentiate apparatus claim from the prior art). The lack of patentable weight notwithstanding, the examiner notes in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8), and therefore the number of input/ouput probes, is an integer, i.e., 18 input/output probes corresponding to the 18 pads/pins of the DUT 106, with 18 being an integer other than a power of two.
Regarding claim 19, Magliocco in view of Waite discloses wherein the plurality of input/output terminals are electrically connected to a plurality of data input/output pads of the devices formed on the wafer (see Magliocco in view of Waite as applied to claim 15, e.g., Magliocco, paragraph 36, DUT 106 can be coupled to test system 100 via a number of pins 108 or via probes (not shown) or contacting pads (not shown) on the substrate; also note in modified Magliocco DUTs 106 are tested while they are still a part of a wafer).
Regarding claim 20, Magliocco in view of Waite discloses wherein the test system is configured to perform the electrical test on the devices formed on the wafer, in parallel (see Magliocco in view of Waite as applied to claim 15, e.g., Magliocco, Fig. 8, test system 100 including tester 102 is configured to perform the electrical test on DUTs 106 in parallel, see Magliocco, Abstract).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Magliocco in view of Waite, and further in view of US 6,477,672 to Satoh (Satoh).
Regarding claim 9, Magliocco in view of Waite discloses wherein the comparative circuit comprises a plurality of comparators configured to generate the plurality of test result signals, and the total number of the plurality of comparators is an integer other than a power of two (see Magliocco in view of Waite as applied to claim 1, noting in Magliocco’s arrangement the total number of the plurality of test signals received from the DUT 106 (e.g., the DUT 106 corresponding to the uppermost test site 104 in Fig. 8) at one time is an integer, i.e., 18 test signals corresponding to the 18 pads/pins of the DUT 106), which implies the total number of the plurality of comparators 126 is also 18, with 18 being an integer other than a power of two).
Magliocco in view of Waite is not relied upon as explicitly disclosing that the plurality of comparators is configured to generate the plurality of test result signals based on results of comparing the plurality of test signals with a test reference voltage. Satoh discloses in connection with Fig. 1 the use of a voltage comparator for determining whether or not a logical value of a response signal outputted from the memory under test MUT has a normal voltage value using a defined voltage value as a test reference voltage (Satoh, e.g., col. 2, line 62 to col. 3, line 4). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Magliocco in view of Waite such that the plurality of comparators is configured to generate the plurality of test result signals based on results of comparing the plurality of test signals with a test reference voltage. In this way, in the manner disclosed by Satoh, it can be determined whether or not a logical value of a response signal outputted from a memory under test has a normal voltage value.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2004/0044938 to Heo relates to a system for testing a plurality of semiconductor devices in parallel at the same time; see, e.g., Fig. 1.
US 2003/0210069 to Kikuchi et al. relates to the implementation of a high efficiency in the memory test for a synchronous DRAM or the like; see, e.g., Fig. 13.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL R MILLER whose telephone number is (571)270-1964. The examiner can normally be reached 9AM-5PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL R MILLER/Primary Examiner, Art Unit 2863
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