DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, without traverse, of species I encompassing claims 1-14 in the “Response to Election / Restriction Filed - 08/04/2026”, is acknowledged.
This office action considers claims 1-24 pending for prosecution, of which, non-elected claims 15-24 are withdrawn, and elected claims 1-14 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (40; Fig 2b; [0068]) = (element 40; Figure No. 2b; Paragraph No. [0068]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation, in this case, Hata may not be preceded by the inventor tag, wherein the other reference citation. For example Pavier, will carry inventor tag. These conventions are used throughout this document.
Claims 1, 3-11 and 14are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Hata; Toshiyuki et al. (US 20080211010 A1) hereinafter referenced as Hata;.
Regarding claim 1, Hata teaches a package (2; Fig 1; [0061]), comprising (see the entire document, figs 1, 5, 9, 11-13 along with other relevant figures, specifically, as cited below):
PNG
media_image1.png
597
1268
media_image1.png
Greyscale
Hata Fig 1 Fig 12 truncated along region 47 of Fig 11
of Fig 11
a single integral electrically conductive (of copper) body (48 of 45; Figs 11-13; [0085];
a first chip (5) with an integrated transistor ([0070], Q2 in fig 9 [0078]) and comprising a first terminal (D2/3, 5) attached on the body (46 of 45), a second terminal (S2/3,3), and a third terminal (G2/3, 4), wherein the second terminal (S2/3,3) and the third terminal (G2/3, 4) are formed on one main surface (top with clip 7) of the first chip (5) and the first terminal (D2/3, 5) is formed on an opposing other main surface (bottom) of the first chip (5), wherein the first terminal (D2/3, 5) is a drain (or collector terminal), the second terminal (S2/3,3) is a source (or emitter terminal), and the third terminal (G2/3, 3) is a gate (or base) terminal;
a second chip (4) with an integrated transistor ([0070], Q1 in fig 9; [0078]) and comprising a fourth terminal (S1/3,7) attached on the body (46 of 45), a fifth terminal (D1/3, 1) and a sixth terminal (G1/3, 8), wherein the fourth terminal (S1/3,7) and the sixth terminal (G1/3, 8) are formed on one main surface of the second chip (4) and the fifth terminal (D1/3, 1) is formed on an opposing other main surface of the second chip (4), wherein the fourth terminal (S1/3,7) is a source or emitter terminal, the fifth terminal (D1/3, 1) is a drain or collector terminal, and the sixth terminal (G1/3, 8) is a gate or base terminal;
a third terminal lead structure (8,4/3) connected with the third terminal (G2/3, 4) by a third terminal connection element (31 wire-bonded to 37); and
a sixth terminal lead structure (8,3/8) connected with the sixth terminal (G1/3, 8) by a sixth terminal connection element (31 wire-bonded to 32),
wherein the first chip (5 with Q2) and the second chip (4 with Q1) are connected to form a half bridge (construed from [0078] the semiconductor device 1 of this embodiment 1 can be also used for a circuit of half bridge construction), and
wherein at least part of one of the third terminal connection element (31 wire-bonded to 37) and the sixth terminal connection element (31 wire-bonded to 32) extends above one main surface of the body (46 or 45) (depicted in Fig 1,12), and at least part of the other one of the third terminal connection element (31 wire-bonded to 37) and the sixth terminal connection element (31 wire-bonded to 32) extends below said main surface (construed from Fig 5 [0061] where some portion of 31 above 4 and some portion below 4 ) of the body (46 or 45).
Regarding claim 3, Hata as applied to the package according to claim 1, further teaches, wherein a surface portion of the body facing away from the first chip (5) and from the second chip (4) forms an exposed exterior package surface (Figs 1,12).
Regarding claim 4, Hata as applied to the package according to claim 1, further teaches, wherein at least one of the third terminal connection element (31 wire-bonded to 37) and the sixth terminal connection element (31 wire-bonded to 32) comprises a bond wire (31) with a loop height which does not exceed a thickness of the single integral electrically conductive body (46 of 45) , wherein in particular the third terminal lead structure (8,3/4) and the sixth terminal lead structure are arranged to face two opposing edges of the body (depicted in Figs 1,12).
Regarding claim 5, Hata as applied to the package according to claim 1, further teaches, comprising a fifth terminal lead structure (8. 7/3) connected with the fifth terminal (S1/3, 7) by an electrically conductive fifth terminal connection element (31 wire-bonded to 30).
Regarding claim 6, Hata as applied to the package according to claim 1, further teaches, comprising a second terminal lead structure (8, 3/3) connected with the second terminal (S2/3,3) by an electrically conductive second terminal connection element (31 wire-bonded to 36).
Regarding claim 7, Hata as applied to the package according to claim 6, further teaches, wherein at least one of the electrically conductive fifth terminal connection element (31 wire-bonded to 30). and the electrically conductive second terminal connection element (31 wire-bonded to 36) comprises a clip (fixing parts 7 or 35 ; [0068,0071).
Regarding claim 8, Hata as applied to the package according to claim 1, further teaches, comprising a common terminals lead structure (49; Fig 12; [0085]) connected with the first terminal (D2/3. 5) and with the fourth terminal (S1/3,7), wherein for example the common terminals lead structure is integrally formed with the body (46 of 45).
Regarding claim 9, Hata as applied to the package according to claim 1, further teaches, comprising an encapsulant (2 of epoxy resin [0061]) at least partially encapsulating (figs 4,5)3 the body (46 of 45), the first chip (5) and the second chip (5).
Regarding claim 10, Hata as applied to the package according to claim 9, further teaches, wherein the encapsulant (138; Figs 2-10) comprises an exterior creepage distance (d, fig 8; [0076-0077]) increasing groove arranged for increasing a creepage distance (g; fig ;[0076]) between the body and lead structures, for example a fifth terminal lead structure connected with the fifth terminal and a second terminal lead structure connected with the second terminal, being spaced with respect to the body.
Regarding claim 11, Hata as applied to the package according to claim 10, further teaches, wherein a main surface of the body facing away from the first chip (5) and the second chip (4) is at least partially exposed beyond the encapsulant (depicted in Fig 8, where at least leads 3 are exposed).
Regarding claim 14, Hata as applied to the package according to claim 1, further teaches, wherein the single integral electrically conductive body (46/45; figs 11-13) is a chip carrier, for example at least one of the group consisting of a leadframe structure ([0085-0087) (, a Direct Copper Bonding substrate, and a Direct Aluminum Bonding substrate).
Claim 2 is rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Hata; Toshiyuki et al. (US 20080211010 A1) hereinafter referenced as Hata with evidence from Ahlers; Dirk et al. (US 0180342447 A1) hereinafter referenced as Ahlers.
Regarding claim 2, Hata as applied to the package according to claim 1, further teaches, wherein the first chip (5 with Q2; fig 1,12, 9) is a low-side chip and the second chip (5 with Q1; fig 1,12, 9) is a high-side chip (the configuration of Fig 9 matches with Ahlers [0021] the first transistor chip is configured as a low-side switch and the second transistor chip is configured as a high-side switch. The terms “low side” and “high side” transistor chips relate to the function of the respective transistor chip in the context of a half bridge application. More specifically, the drain terminal of a low side field effect transistor chip may be directly connected via the chip carrier with a source terminal of a high side field effect transistor chip). In this case, the drain terminal ((D2/3, 5) of a low side field effect transistor chip (5) directly being connected via the chip carrier with (46 or 45) a source terminal of a high side field effect transistor chip.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hata; Toshiyuki et al. (US 20080211010 A1) hereinafter referenced as Hata; in view of PAVIER; Mark et al. (US 20190006260 A1) hereinafter referenced as Pavier
Regarding claims 12-13, Hata as applied to the package according to claim 11 and or claim 12, does not expressly disclose,
For claim11: comprising a thermal interface material on at least part of the exposed main surface of the body (46 of 45).
For claim 13: at least one of the following features:
the package comprising an electrically insulating foil on the thermal interface material;
the package comprising a heat sink on the thermal interface material or on the electrically insulating foil.
However, in the analogous art, Pavier teaches a package configured as a half bridge consisting of a lead frame connected power module ([0046-0047]), wherein (Fig 3; [0101]) the top surface of the package 100 is flat and co-planar with the back surface an exposed metalized surface ( at backside) that is designed for interfacing with heatsink 132. The exposed metalized surface is part of the chip carrier 102 configured as active metal brazed circuit onto which the electronic chips 104, embodied as power semiconductor dice, are mounted. The exposed surface may be finished in a material (compare layer 130) that is suitable for connecting the package 100 to heatsink 132. To obtain a very low thermal resistance, a silver sintered interconnect can be formed using layer 130. Alternatively, other thermal interface materials (TIM) such as thermal grease or solder can be used.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the TIM and heat sink component to Hata’s (46 of 45), and thereafter the combination of (Hata and Pavier) teaches the subject matter as claimed in claims 12 and 13, since, this inclusion, at least, allows for increased heat spreading underneath the electronic chips, being here embodied as power semiconductor dice, and reduced electrical conduction losses in the current path between the back of the two electronic chips and the collector terminals (Pavier [0111])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
September 12, 2026
Prosecution Insights