DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 9, 10, 12, 13-15, and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0031318 A1 (Brown).
Brown discloses, referring primarily to figures 3-5K, a method for fabricating a monolithic multi-layered circuit board (102) having at least one internal coaxial via (220), the method comprising: determining a target depth (510) of an outer conductor (512) for an internal coaxial via of the monolithic multi-layered circuit board, wherein the target depth is above an internal signal layer (504) of the monolithic multi-layered circuit board; fabricating the outer conductor to the target depth (figure 5C); fabricating a dielectric insulator (516) for the internal coaxial via; and fabricating an inner conductor (520) for the internal coaxial via, wherein the inner conductor is electrically coupled to a signal connection pad located on the internal signal layer ([0034]) [claim 1], further comprising removing any excess portion of the inner conductor below the internal signal layer, while leaving a connection between the inner conductor and the signal connection pad intact (figure 5K; [0034]) [claim 2], wherein: determining the target depth includes determining a depth of a reference plane defined by a reference layer of the monolithic multi-layered circuit board proximate to the signal connection pad ([0029]); fabricating the outer conductor comprises: forming a top cavity (510) to the target depth, the top cavity having an outer diameter of the internal coaxial via; forming a pilot hole (508), coaxial with the top cavity, through a remainder of the monolithic multi-layered circuit board; coating the top cavity including a floor of the top cavity and the pilot hole to form a conductive cylinder (512, figure 5C); and drilling the conductive cylinder to a depth sufficient to disconnect the conductive cylinder from the pilot hole thereby forming the outer conductor of the internal coaxial via (figure 5K); fabricating the dielectric insulator includes filling the top cavity with a dielectric material (516); and fabricating the inner conductor includes: forming an inner hole (518; figure 5F) through the dielectric material for housing the inner conductor, wherein the inner hole is a through hole penetrating the signal connection pad and the remainder of the monolithic multi-layered circuit board; and coating the inner hole (520) with a conductive material to form the inner conductor [claim 3], wherein removal of the excess portion of the inner conductor below the signal connection pad includes counter-drilling from a bottom surface of the monolithic multi-layered circuit board (5K; [0034]) [claim 6], further comprising forming one or more upper connection pads (528) for the internal coaxial via on an upper surface of the monolithic multi-layered circuit board [claim 9], wherein the target depth is determined by measuring a depth of the internal signal layer from an upper surface of the monolithic multi-layered circuit board using a cross-sectioned sacrificial sample monolithic multi-layered circuit board ([0034]).
Regarding claim 10, the Examiner notes that the limitation “wherein the monolithic multi-layered circuit board is part of a test system interposer for testing semiconductor devices” is directed to the method of using the device and not the method by which the device is made. Thus it is only considered to the extent to which the method of using impacts the method of producing the device.
Furthermore, Brown discloses, a monolithic multi-layered circuit board (102) having one or more internal coaxial vias (220) for electrically coupling an upper surface layer to one or more internal signal layers (238) within the monolithic multi-layered circuit board, wherein each of the one or more internal coaxial vias comprises: an upper cavity (510) housing an outer conductor (512), wherein a bottom of the upper cavity is at a target depth within the monolithic multi-layered circuit board, wherein the target depth is above an internal signal layer (504) of the monolithic multi-layered circuit board, and wherein a diameter of the upper cavity determines an outer diameter of the outer conductor; an inner conductor (520) configured to electrically transmit a signal from the upper surface layer to the internal signal layer; and a dielectric insulator (516) located between the outer conductor and the inner conductor [claim 12], wherein the upper cavity is formed using a drill, wherein the target depth is determined relative to a reference plane, and wherein the reference plane is determined by electrical continuity between the reference plane and the drill ([0034]) [claim 13], wherein a lower end of the inner conductor is formed by removing the excess below the signal connection pad by counter drilling from a bottom surface of the monolithic multi-layered circuit board (figure 5K; [0034]) [claim 15], further comprising a plurality of upper connection pads (528) on the upper surface of the monolithic multi-layered circuit board for the one or more internal coaxial vias (figure 4) [claim 18].
Regarding claim 14, the Examiner notes that the limitation “wherein the outer conductor is initially formed by electroless plating and wherein the outer conductor is built to a desired wall thickness by electroplating” [claim 14] is a process limitation in a product claim and thus has only been considered to the extent to which said process impacts the structure of the device (MPEP 2113).
Regarding claim 17, the Examiner notes the limitation “wherein the inner conductor is initially formed by electroless plating and wherein the inner conductor is built to a desired thickness by electroplating” [claim 17] is a process limitation in a product claim and thus has only been considered to the extent to which said process impacts the structure of the device (MPEP 2113).
Regarding claim 19, the Examiner note that the limitation “wherein the monolithic multi-layered circuit board is part of a test system interposer for testing semiconductor devices” is directed to the manner in which the device is employed and not an inherent feature of the device.
Regarding claim 20 the Examiner notes that the limitation “wherein the target depth of the upper cavity is determined by measuring a depth of the internal signal layer from the upper surface layer using a cross-sectioned sacrificial sample monolithic multi-layered circuit board” [claim 20] is a process limitation in a product claim and thus has only been considered to the extent to which said process impacts the structure of the device (MPEP 2113).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown in view of US 2005/0128672 (Tourne).
Regarding claim 4, Brown discloses the claimed invention as described above except Brown does not specifically state that the top cavity is formed using a drill and wherein the depth of the reference plane is determined by electrical continuity between the reference plane and the drill [claim 4]. However, such a feedback based method of drilling is well known in the art as evidenced by Tourne ([0018]). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Brown as is known in the art and evidenced by Tourne. The motivation for doing so would have been use a method known for achieving proper drilling depth (Tourne [0018])
Claim(s) 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown in view of US 2009/0321126 A1 (Chandrasekraran).
Regarding claim 5, Brown discloses the claimed invention as described above with respect to claim 3 except Brown does not specifically state that “the conductive cylinder is initially formed by electroless plating and wherein the conductive cylinder is built to a desired wall thickness by electroplating [claim 5].” However, such a method of via formation is well known in the art as evidenced by Chandrasekraran ([0028]). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Brown. The motivation for doing so would have been to ensure desire conductor thickness.
Regarding claim 8, Brown discloses the claimed invention as described above with respect to claim 3 except Brown does not specifically state that “the inner conductor is initially formed by electroless plating and wherein the inner conductor is built to a desired thickness by electroplating [claim 8].” However, such a method of via formation is well known in the art as evidenced by Chandrasekraran ([0028]). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Brown. The motivation for doing so would have been to ensure desire conductor thickness.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown in view of US 2025/0168989 (Weaver).
Regarding claim 7, Brown discloses the claimed invention as described above with respect to claim 6 except Brown does not specifically disclose “filling a lower cavity formed by the counter-drilling with an insulating material [claim 7].” However, it is well known in the art to backfill backdrilled vias with an insulating material as evidenced by Weaver (figure 4; 8, figure 5). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Brown. The motivation for doing so would have been to prevent debris intrusion (Weaver [0023]-[0025]).
Regarding claim 16, Brown discloses the claimed invention as described above with respect to claim 15 except Brown does not specifically disclose that “a lower cavity between the lower end of the inner conductor and the bottom surface of the monolithic multi-layered circuit board is filled with an insulating material [claim 16].” However, it is well known in the art to backfill backdrilled vias with an insulating material as evidenced by Weaver (figure 4; 8, figure 5). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Brown. The motivation for doing so would have been to prevent debris intrusion (Weaver [0023]-[0025]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JEREMY C. NORRIS
Examiner
Art Unit 2847
/JEREMY C NORRIS/Primary Examiner, Art Unit 2847