Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Structure of a Planar MOS-gated Semiconductor Device Having Multiple Hexagonal Active Region Units Surrounding a Non-Active Region”
because the revised title more accurately reflects the subject matter of independent claim 1 by emphasizing the claimed arrangement of multiple hexagonal active region units surrounding a non-active region, rather than merely identifying the device as a planar MOS-gated semiconductor device.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 8-10 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banerjee et al. (US 20180047844).
Regarding claim 1. Fig 7 (a detail view of Fig 8) and Fig 8 of Banerjee discloses A structure of a planar metal-oxide-semiconductor-gated semiconductor [0074] device having an active region (Fig 8: Active cell) and a non-active region (Fig 8: Contact cell), wherein the active region comprises:
multiple hexagonal active region units [0090], which are arranged closely adjacent to each other to cover the active region, and form a plane of the active region (Fig 7, Fig 8);
wherein the hexagonal active region units surround the non-active region (Fig 7, Fig 8, [0090]: ‘hexagonal contact cell is surrounded by 6 hexagonal active cell’), and
the non-active region is connected to at least one of the hexagonal active region units (Fig 7, Fig 8); and
the active region comprises a channel formed by MOS structure in inversion or accumulation [0074], while the non-active region does not comprise a channel [0090].
Regarding claim 2. Banerjee discloses The structure according to claim 1, wherein the non-active region has one or multiple hexagonal non-active region units, the hexagonal active region units surround the non-active region, and the hexagonal non-active region unit is connected to at least one of the one or multiple hexagonal active region units (Fig 7).
Regarding claim 4. Banerjee discloses The structure according to claim 1, wherein each of the hexagonal active region units comprises:
a first JFET region [0090]; and
a first first-type semiconductor well; wherein the first JFET region is a hexagonal region, the first first-type semiconductor well starts to surround the first JFET region from edges of the hexagonal active region units, and the first JFET region is disposed in the first first-type semiconductor well or between adjacent two of the first first-type semiconductor wells ([0090]: the active cell contains the JFET region, the active MOSFET channel and N+ regions).
Regarding claim 5. Banerjee discloses The structure according to claim 2, wherein each of the hexagonal active region units comprises:
a first JFET region [0090]; and a first first-type semiconductor well;
wherein the first JFET region is a hexagonal region, the first first-type semiconductor well starts to surround the first JFET region from edges of the hexagonal active region units, and the first JFET region is disposed in the first first-type semiconductor well or between adjacent two of the first first-type semiconductor wells (Banerjee expressly discloses that each active cell comprises a JFET region in a central portion of the semiconductor cell and a well region of a second conductivity type circumscribing the JFET region, with the source region formed in the well region. Fig. 1A and the associated description further illustrate that the well region extends from the peripheral portion of the active cell to surround the JFET region).
Regarding claim 8. Banerjee discloses The structure according to claim 4, wherein a cross section of the hexagonal active region units comprises:
a first source metal; a first dielectric region having an upper surface covered by the first source metal; a gate having an upper surface covered by the first dielectric region; a second dielectric region having an upper surface covered by a bottom surface of the gate; a first high concentration second-type semiconductor region having an upper surface contacting a bottom surface of the second dielectric region, wherein a bottom surface of the first high concentration second-type semiconductor region contacts the first first-type semiconductor well, and the first first-type semiconductor well covers the first high concentration second-type semiconductor region; a first second-type semiconductor region covering a sidewall and a bottom surface of the first first-type semiconductor well; and a first drain metal covered by a bottom surface of the first second-type semiconductor region; wherein a distance from an edge of the first first-type semiconductor well to an edge of the first high concentration second-type semiconductor region covered by the first first-type semiconductor well is a channel length (Banerjee expressly discloses that each active cell comprises a JFET region, a well region, a source region, a gate dielectric layer, a gate electrode, and an interlayer dielectric, wherein the source region is formed in the well region and the well region circumscribes the JFET region (Figs. 1A-1E; [0033]-[0040]). The cross-sectional views of Figures 1B-1E illustrate the corresponding source metal, interlayer dielectric, gate electrode, gate dielectric, source region, well region, drift region, and drain structure recited in the claim 8.
Banerjee further discloses that current flows vertically from the drain through the drift region into the JFET region, changes direction at the semiconductor-dielectric interface (the accumulation region), and then flows laterally through the MOSFET channel adjacent to the JFET region before entering the source region [0074]. Thus, Banerjee expressly identifies the channel as the region beneath the gate dielectric between the source region and the JFET region.
Moreover, Banerjee expressly identifies the channel length as a device design parameter of the MOSFET unit cell and teaches that the cell pitch is defined, in part, by the JFET region width and the channel length [0076]. Figures 1B-1E illustrate that the channel length corresponds to the distance between the edge of the well region and the edge of the heavily doped source region beneath the gate dielectric. Accordingly, Banerjee discloses the claimed limitation that the distance from the edge of the first first-type semiconductor well to the edge of the first high concentration second-type semiconductor region covered by the first first-type semiconductor well is a channel length).
Regarding claim 9. Banerjee discloses The structure according to claim 5, wherein a cross section of the hexagonal active region units comprises:
a first source metal; a first dielectric region having an upper surface covered by the first source metal; a gate having an upper surface covered by the first dielectric region; a second dielectric region having an upper surface covered by a bottom surface of the gate; a first high concentration second-type semiconductor region having an upper surface contacting a bottom surface of the second dielectric region, wherein a bottom surface of the first high concentration second-type semiconductor region contacts the first first-type semiconductor well, and the first first-type semiconductor well covers the first high concentration second-type semiconductor region; a first second-type semiconductor region covering a sidewall and a bottom surface of the first first-type semiconductor well; and a first drain metal covered by a bottom surface of the first second-type semiconductor region; wherein a distance from an edge of the first first-type semiconductor well to an edge of the first high concentration second-type semiconductor region covered by the first first-type semiconductor well is a channel length (Banerjee expressly discloses that each active cell comprises a JFET region disposed in a central portion of the semiconductor cell, a well region circumscribing the JFET region, a source region formed in the well region, a gate dielectric layer, a gate electrode, and an interlayer dielectric (Figs. 1A-1E; [0033]-[0040]). The cross-sectional views of Figures 1B-1E further illustrate the corresponding source metal, interlayer dielectric, gate electrode, gate dielectric, source region, well region, drift region, and drain structure recited in the claim 9 (Banerjee further discloses that current flows vertically from the drain through the drift region into the JFET region, changes direction at the semiconductor-dielectric interface defining the accumulation region, and then flows laterally through the MOSFET channel adjacent the JFET region before entering the source region [0074]. Accordingly, Banerjee expressly identifies the channel as the semiconductor region beneath the gate dielectric between the source region and the JFET region.
Moreover, Banerjee expressly identifies the channel length as a device design parameter of the MOSFET unit cell and teaches that the cell pitch is defined, in part, by the JFET region width and the channel length [0076]. Figures 1B-1E illustrate that the channel length corresponds to the distance between the edge of the well region and the edge of the heavily doped source region beneath the gate dielectric. Accordingly, Banerjee discloses the claimed limitation that the distance from the edge of the first first-type semiconductor well to the edge of the first high concentration second-type semiconductor region covered by the first first-type semiconductor well is a channel length).
Regarding claim 18. Banerjee discloses The structure according to claim 1, wherein the planar metal-oxide-semiconductor-gated semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET) [0074] or an insulated gate bipolar transistor (IGBT).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 6, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Banerjee et al. (US 20180047844) in view of Sugawara et al. (US 20180248008).
Regarding claim 3. Banerjee discloses The structure according to claim 2. But Banerjee does not expressly disclose wherein the non-active region has the multiple hexagonal non-active region units arranged closely adjacent to each other, but there is no independent one of the hexagonal non-active region units being surrounded by the multiple hexagonal non-active region units.
However, Sugawara discloses a semiconductor device including multiple active regions (RA) and multiple contact regions (RC) arranged in a repeating cellular layout. Figure 6 illustrates the individual active region (RA) and contact region (RC), while Figure 9 illustrates the overall repeating arrangement of the active regions (RA) and contact regions (RC). As described in paragraphs [0077]-[0079], the active regions (RA) and contact regions (RC) are regularly displaced to form a repeating mesh arrangement extending across the semiconductor device. Accordingly, Sugawara discloses multiple non-active region units (RC) disposed among multiple active regions (RA).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Banerjee's repeating hexagonal active cell/contact cell layout by arranging the contact cells in the repeating manner taught by Sugawara so as to provide a repeating cellular layout across the semiconductor device. Such a modification merely applies a known arrangement of active and contact regions to another known cellular MOS layout and would have predictably yielded a semiconductor device having multiple non-active region units while preserving the operation of the MOS device.
Regarding claim 6. Banerjee in view of Sugawara discloses The structure according to claim 3, Banerjee discloses wherein each of the hexagonal active region units comprises:
a first JFET region; and a first first-type semiconductor well; wherein the first JFET region is a hexagonal region, the first first-type semiconductor well starts to surround the first JFET region from edges of the hexagonal active region units, and the first JFET region is disposed in the first first-type semiconductor well or between adjacent two of the first first-type semiconductor wells (Fig 7, [0090]).
Regarding claim 10. Banerjee in view of Sugawara discloses The structure according to claim 6, wherein a cross section of the hexagonal active region units comprises:
a first source metal; a first dielectric region having an upper surface covered by the first source metal; a gate having an upper surface covered by the first dielectric region; a second dielectric region having an upper surface covered by a bottom surface of the gate; a first high concentration second-type semiconductor region having an upper surface contacting a bottom surface of the second dielectric region, wherein a bottom surface of the first high concentration second-type semiconductor region contacts the first first-type semiconductor well, and the first first-type semiconductor well covers the first high concentration second-type semiconductor region; a first second-type semiconductor region covering a sidewall and a bottom surface of the first first-type semiconductor well; and a first drain metal covered by a bottom surface of the first second-type semiconductor region; wherein a distance from an edge of the first first-type semiconductor well to an edge of the first high concentration second-type semiconductor region covered by the first first-type semiconductor well is a channel length (Banerjee expressly discloses that each active cell comprises a JFET region disposed in a central portion of the semiconductor cell, a well region circumscribing the JFET region, a source region formed in the well region, a gate dielectric layer, a gate electrode, and an interlayer dielectric (Figs. 1A-1E; [0033]-[0040]). The cross-sectional views of Figures 1B-1E further illustrate the corresponding source metal, interlayer dielectric, gate electrode, gate dielectric, source region, well region, drift region, and drain structure recited in the claim 10. Banerjee further discloses that current flows vertically from the drain through the drift region into the JFET region, changes direction at the semiconductor-dielectric interface defining the accumulation region, and then flows laterally through the MOSFET channel adjacent the JFET region before entering the source region [0074]. Moreover, Banerjee expressly identifies the channel length as a device design parameter of the MOSFET unit cell and teaches that the cell pitch is defined, in part, by the JFET region width and the channel length [0076]. Figures 1B-1E illustrate that the channel length corresponds to the distance between the edge of the well region and the edge of the heavily doped source region beneath the gate dielectric. Accordingly, Banerjee discloses the additional cross-sectional limitations of the claim 10.
As discussed with respect to the claim 6, Sugawara discloses the arrangement of multiple non-active region units among the active region units (Fig. 6; Fig. 9; [0077]-[0079]), thereby the additional limitation is disclosed by the claim 10 through the claim 6.
Regarding claim 17. Banerjee discloses The structure according to claim 3. But Banerjee does not expressly disclose wherein the structure has the multiple hexagonal non-active region units being the three hexagonal non-active region units arranged closely adjacent to each other; wherein the high concentration first-type semiconductor regions of the three hexagonal non-active region units are arranged closely adjacent to each other, and the metal-semiconductor contact regions of the three hexagonal non-active region units are arranged closely adjacent to each other.
However, Sugawara discloses a semiconductor device including hexagonal contact regions (RC) arranged in a repeating cellular layout. Figure 6 illustrates that three adjacent hexagonal contact regions (RC) are arranged closely adjacent to one another. Figure 15 further illustrates that each contact region includes a protective diffusion layer (306) disposed beneath the contact electrode (5). Paragraph [0055] expressly discloses that the protective diffusion layer (306) is higher in p-type impurity concentration than the base region (302). Accordingly, the protective diffusion layer (306) corresponds to the claimed high concentration first-type semiconductor region, and the contact electrode (5) contacting the protective diffusion layer (306) corresponds to the claimed metal-semiconductor contact region. Thus, Sugawara discloses that the high concentration first-type semiconductor regions and the corresponding metal-semiconductor contact regions of the three adjacent hexagonal non-active region units are arranged closely adjacent to each other.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Banerjee's repeating hexagonal cellular layout with the adjacent arrangement of three hexagonal non-active region units taught by Sugawara in order to provide a repeating cellular layout having closely adjacent non-active region units while preserving the known operation of the semiconductor device. Such modification would have predictably resulted in the semiconductor device recited in the claim 17.
Allowable Subject Matter
Claims 7 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, the claimed hexagonal non-active region unit recited in the claim 7. In particular, the prior art fails to teach or suggest a hexagonal non-active region unit comprising a polycrystalline gate opening region, a second first-type semiconductor well, a metal-semiconductor contact region, and a high-concentration first-type semiconductor region, wherein the second first-type semiconductor well is disposed in the polycrystalline gate opening region and surrounds the metal-semiconductor contact region, the high-concentration first-type semiconductor region contacts the metal-semiconductor contact region, and the combination of the second first-type semiconductor well and the high-concentration first-type semiconductor region entirely covers the planar extent of the non-active region, as recited in the claim 7.
Banerjee discloses a contact cell including semiconductor layers, heavily doped semiconductor regions, and a source ohmic contact. However, Banerjee does not disclose or suggest the claimed structural configuration of the hexagonal non-active region unit, including the surrounding first-type semiconductor well, the relationship between the metal-semiconductor contact region and the high-concentration first-type semiconductor region, or the claimed complete planar coverage of the non-active region by the combination of the first-type semiconductor well and the high-concentration first-type semiconductor region.
Sugawara discloses repeating active regions and contact regions arranged in a cellular layout but does not disclose or suggest the claimed internal structure of the non-active region unit or the recited geometric and structural relationships among the polycrystalline gate opening region, semiconductor well, metal-semiconductor contact region, and high-concentration first-type semiconductor region.
Accordingly, the prior art of record does not teach or suggest the particular structural configuration of the hexagonal non-active region unit recited in the claim 7.
Regarding claim 14. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, the claimed cross-sectional structure of the hexagonal non-active region unit recited in claim 14. In particular, the prior art fails to teach or suggest a second first-type semiconductor well connected to the first first-type semiconductor well, a high-concentration first-type semiconductor region contacting the second first-type semiconductor well, and a second second-type semiconductor region connected to the first second-type semiconductor region, wherein a region formed by the combination of the second first-type semiconductor well and the high-concentration first-type semiconductor region entirely covers the non-active region, the range of the second source metal defines the polycrystalline gate opening region, and the range of the second source metal exclusive of the third dielectric region defines the metal-semiconductor contact region, as recited in the claim 14.
Banerjee discloses a contact cell including semiconductor layers, heavily doped regions, and a source ohmic contact. However, Banerjee does not disclose or suggest the claimed structural relationships defining the entire planar extent of the non-active region by the combination of the semiconductor well and the high-concentration semiconductor region, nor does Banerjee disclose the claimed definition of the polycrystalline gate opening region and the metal-semiconductor contact region based on the extent of the source metal.
Sugawara discloses contact regions arranged in a repeating cellular layout but likewise fails to disclose or suggest the claimed cross-sectional configuration and planar relationships of the non-active region unit.
Accordingly, the prior art of record does not teach or suggest the particular cross-sectional configuration of the hexagonal non-active region unit recited in the claim 14.
Regarding claim 15. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, suggest a hexagonal non-active region unit comprising a Schottky contact region and a second JFET region, wherein the Schottky contact region is disposed between the second JFET region and the second polycrystalline gate opening region, and a range of the Schottky contact region is smaller than the third first-type semiconductor well, as recited in the claim 15.
Banerjee discloses integrating a Schottky contact into a MOSFET cell and teaches that a rectifying Schottky contact is formed between a metal layer and the drift region ([0098]-[0100]). However, Banerjee does not disclose or suggest the claimed structural relationship in which the Schottky contact region is surrounded by a first-type semiconductor well having a larger planar extent, nor does Banerjee disclose the claimed arrangement within a hexagonal non-active region unit.
Sugawara discloses repeating active regions and contact regions arranged in a cellular layout but does not disclose or suggest an integrated Schottky contact region, a JFET region within the non-active region unit, or the claimed size relationship between the Schottky contact region and the surrounding first-type semiconductor well.
Accordingly, the prior art of record does not teach or suggest the particular structural configuration of the hexagonal non-active region unit recited in the claim 15.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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