DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-18 are pending.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to JP2021-192779 for 11/29/2021. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: LEAD FRAME DEVICE HAVING AN ISOLATION ELEMENT DISPOSED BETWEEN CONTROL AND DRIVE ELEMENTS
The disclosure is objected to because of the following informalities:
The specification of the instant application makes reference to an “insulating element,” an “insulation transformer,” and a “capacitive insulating element.” Examiner believes this is in error, due to translation from Japanese to English, and that the appropriate terminology would be “isolation element,” “isolation transformer,” and “capacitive isolation element,” to match the meaning of the elements described in the specification and shown in the figures. All instances of this error should be amended. This is further verified through machine translation of the corresponding PCT application WO2023/095659A1, which makes reference to an “isolation element,” included for reference.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 currently makes reference to an “insulating element” which is electrically connected. In light of the specification, paragraph beginning on page 5 line 30, the applicant appears to intend the “insulating element” to be either an “insulation transformer” (Fig. 10) or a “capacitive insulating element,” terms not well-known in the art. However, “isolation transformers” and “capacitive isolation elements” are well-known in the art. In light of the specification, examiner believes there is sufficient clarity to support that the claim wording is a translation error, and should be amended to read “isolation element,” providing “isolation,” not insulation. This is further verified through machine translation of the corresponding PCT application WO2023/095659A1, which makes reference to an “isolation element,” included for reference. Appropriate changes should be made to all claims containing this error.
Appropriate correction is required.
Claim Interpretation
For purposes of examination, and in light of the disclosure of the specification, the “insulating element” of claims 1-18 will be interpreted as an “isolation element” providing “isolation.” See details above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 9, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. (US PGPub 2020/0066619; herein known as Matsubara) in view of Ragonese et al. (An Experimental Comparison of Galvanically Isolated DC-DC Converters: Isolation Technology and Integration Approach; herein known as Ragonese, and provided herein for reference), and further in view of Schaller et al. (US PGPub 2021/0005539; herein known as Schaller).
Regarding claim 1, Matsubara teaches (Fig. 7) a semiconductor device comprising: a die pad (2, [0035]); a first semiconductor element (111, [0036]) and a second semiconductor element (112, [0035]) each mounted on the die pad ([0035]); an insulating element (12, [0036]) electrically connected (712, 713, [0077]) to the first semiconductor element and the second semiconductor element and insulating the first semiconductor element and the second semiconductor element from each other ([0034]);
Matsubara does not explicitly teach: a dummy element bonded to the die pad; and a first bonding layer bonding the dummy element and the insulating element, wherein the dummy element includes an insulating layer located between the die pad and the first bonding layer in a thickness direction.
Ragonese teaches (annotated Fig. 6b below) a dummy element (DE, [Page 4, paragraph 1]) bonded to the die pad (see Fig. 7b for relationship to leadframe); wherein the dummy element includes an insulating layer (IL, [Page 5, paragraph 2])
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Because Matsubara and Ragonese are both directed toward galvanic isolation, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Matsubara and Ragonese to include a dummy element bonded to the die pad wherein the dummy element includes an insulating layer in order to provide high dielectric strength while maintaining high magnetic coupling (Ragonese, [Page 5, paragraph 2]) in addition to maintaining high efficiency of an isolation transformer (Ragonese, [Page 4, paragraph 1]).
Matsubara in view of Ragonese does not explicitly teach a first bonding layer bonding the dummy element and the insulating element, but does teach wherein use of a bonding layer (77) to adhere two features in a stack is a known technique with the predictable result of providing improved adhesion between two features. Matsubara in view of Ragonese additionally teaches two elements in a stack, one of which is an insulating layer, and one of which is a semiconductor layer.
The disclosure of the instant application does not teach an unexpected result of providing a first bonding layer bonding the dummy element and the insulating element.
Schaller teaches a known technique of providing a first bonding layer (10B, [0030]) bonding two elements in a stack, one of which is an insulating layer (8A, [0030]), and one of which is a semiconductor layer (6A, [0030]), with the predictable result of providing improved adhesion between two features.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Matsubara in view of Ragonese and of Schaller to include a first bonding layer bonding the dummy element and the insulating element to provide improved adhesion between the two layers, yielding the predictable result of adhesion between the two layers. See MPEP 2143.I(C).
Regarding claim 2, Matsubara in view of Ragonese and SCHALLER teaches (Ragonese, annotated Fig. 6b above) the semiconductor device according to claim 1, wherein the dummy element (DE) includes a semiconductor substrate (Ragonese, LCS, [Page 4, paragraph 1]), and the insulating layer (IL) is layered on the semiconductor substrate (see annotated Fig. 6b above).
Regarding claim 3, Matsubara in view of Ragonese and SCHALLER teaches (Matsubara, Fig. 7) the semiconductor device according to claim 2, further comprising a second bonding layer (72, [0032]) bonding the die pad (2, [0035]) and the dummy element (Ragonese, annotated Fig. 6b above, DE).
Regarding claim 4, Matsubara in view of Ragonese and Schaller teaches the semiconductor device according to claim 3, wherein the first bonding layer (Schaller, 8A, [0030]) and the second bonding layer (Matsubara, 72, [0032]) are conductors (Matsubara, [0032], Schaller, [0019]).
Regarding claim 5, Matsubara in view of Ragonese and SCHALLER teaches (Ragonese, annotated Fig. 6b above) the semiconductor device according to claim 3, wherein the insulating layer (IL) is located between the semiconductor substrate (LCS) and the first bonding layer.
Regarding claim 8, Matsubara in view of Ragonese and SCHALLER teaches the semiconductor device according to claim 3, but does not explicitly teach wherein the insulating layer is located between the second bonding layer the semiconductor substrate.
Matsubara in view of Ragonese and SCHALLER does teach wherein the insulating layer is located between the semiconductor substrate and the first bonding layer.
The specification of the instant application does not indicate that the claimed arrangement would operate differently than the embodiment of the prior art, and is simply a variation of an embodiment based on design choice. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that including wherein the insulating layer is located between the semiconductor substrate and the first bonding layer constitutes rearrangement of parts for the purpose of providing dielectric insulation, without an unexpected result. See MPEP 2144.04.VI.C.
Regarding claim 9, Matsubara in view of Ragonese and SCHALLER teaches the semiconductor device according to claim 3, wherein the first layer is located between the semiconductor substrate and the first bonding layer, but does not explicitly teach wherein the insulating layer includes a second layer spaced apart from the first layer, and the second layer is located between the second bonding layer and the semiconductor substrate.
Matsubara in view of Ragonese and SCHALLER does teach wherein an insulating layer is located between the semiconductor substrate and the first bonding layer.
The specification of the instant application does not indicate that the claimed arrangement would operate differently than the embodiment of the prior art, and is simply a variation of an embodiment based on design choice. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that including wherein the insulating layer includes a second layer spaced apart from the first layer, and the second layer is located between the second bonding layer and the semiconductor substrate constitutes rearrangement of parts for the purpose of providing additional dielectric insulation, without an unexpected result. See MPEP 2144.04.VI.C.
Regarding claim 16, Matsubara in view of Ragonese and SCHALLER teach (Matsubara, Fig. 7) the semiconductor device according to claim 1, wherein the die pad (2, [0035]) includes a first die pad (21, [0035]) on which the first semiconductor element (111, [0035]) is mounted and a second die pad (22, [0035]) which is spaced apart from the first die pad and on which the second semiconductor element (112, [0035]) is mounted, and the dummy element (12, [0035], Ragonese, DE) is bonded to the first die pad (21).
Regarding claim 17, Matsubara in view of Ragonese and SCHALLER teach (Matsubara, Fig. 7) wherein a voltage applied to the second semiconductor element (112, [0033]) is higher than a voltage applied to the first semiconductor element (111, [0033]) (voltage applied to the control element is lower than voltage applied to the drive element, [0033]). Examiner notes that the applicant appears to intend to utilize functional language in this claim, as opposed to the current "method of using" language. Thus, it will be interpreted that the semiconductor device is configured to have a higher voltage applied to the second semiconductor element than the first semiconductor element.
Regarding claim 18, Matsubara in view of Ragonese and SCHALLER teach (Matsubara, Fig. 7) the semiconductor device according to claim 16, further comprising: a plurality of first terminals (31, [0041]) electrically connected to the first semiconductor element (111) and a plurality of second terminals (41, [0046]) electrically connected to the second semiconductor element (112), wherein the plurality of first terminals are located opposite to the second semiconductor element with respect to the insulating element (12, [0034]), and the plurality of second terminals are located opposite to the first semiconductor element with respect to the insulating element. The terminals are located at a left- and right-hand side of the insulating element, respectively.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara in view of Ragonese and Schaller as applied to claim 5 above, and further in view of Lin et al. (US Patent 10,242,964; herein known as Lin).
Regarding claim 6, Matsubara in view of Ragonese and Schaller teach the semiconductor device according to claim 5, wherein the dummy element is formed, but does not explicitly teach a protrusion protruding from the insulating layer in the thickness direction, and the protrusion is located outside the first bonding layer as viewed in the thickness direction.
Lin teaches (Fig. 21) a protrusion (30, [Col 10, Line 10]) protruding from the insulating layer (511, [Col 9, Line 56]) in the thickness direction, and the protrusion is located outside the first bonding layer (611, [Col 9 Line 56]) as viewed in the thickness direction.
Because Matsubara in view of Ragonese and Schaller and Lin are directed toward bonding of elements, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Matsubara in view of Ragonese and Schaller and of Lin to include protrusion protruding from the insulating layer in the thickness direction, and the protrusion is located outside the first bonding layer as viewed in the thickness direction in order to avoid microcracks at the corners of the material interfaces (Lin, [Col 18, Line 33]).
Regarding claim 7, Matsubara in view of Ragonese and Schaller and Lin teach (Lin, Fig. 21) wherein the protrusion (30) surrounds the first bonding layer (611). See Figure.
Claims 10-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara in view of Ragonese and Schaller as applied to claim 5 above, and further in view of Haga et al. (US PGPub 2020/0144379; herein known as Haga).
Regarding claim 10, Matsubara in view of Ragonese and Schaller (Ragonese, annotated Fig. 6b below) teaches the semiconductor device according to claim 5, wherein the semiconductor substrate includes a first surface (S1) facing in the thickness direction and opposed to the first bonding layer, a second surface (S2) facing away from the first surface in the thickness direction, and a third surface (S3) facing in a direction orthogonal to the thickness direction, but does not explicitly teach the semiconductor substrate is formed with a first recess recessed from the second surface and the third surface.
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Haga teaches (Fig. 30) the semiconductor substrate (11, [0097]) is formed with a first recess (111B, [0097]) recessed from the second surface (10B, [0097]) and the third surface (10C, [0097]).
Because Matsubara in view of Ragonese and Schaller and Haga are directed toward lead frame packages, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Matsubara in view of Ragonese and Schaller and of Haga to include the semiconductor substrate formed with a first recess recessed from the second surface and the third surface in order to inhibit connection failures of electrodes by preventing capillary action of bonding layers surrounding a substrate (Haga, [0093]).
Regarding claim 11, Matsubara in view of Ragonese, Schaller, and Haga teaches (Haga, Fig. 30) the semiconductor device according to claim 10, wherein the first recess (111B, [0097]) surrounds the second surface (10B, formed in a grid, [0100]).
Regarding claim 12, Matsubara in view of Ragonese, Schaller, and Haga teaches (Haga, Fig. 30) the semiconductor device according to claim 10, wherein the semiconductor substrate (11, [0097]) is formed with a second recess (111A, [0097]) recessed from the first surface (top surface) and the third surface (10C, [0097]), and the second recess overlaps with the first recess as viewed in the thickness direction (see figure).
Regarding claim 13, Matsubara in view of Ragonese, Schaller, and Haga teaches (Haga, Fig. 30) the semiconductor device according to claim 12, wherein the second recess (111A, [0097]) surrounds the first surface (formed in a grid, [0100]).
Regarding claim 15, Matsubara in view of Ragonese, Schaller, and Haga teaches the semiconductor device according to claim 10, wherein the second bonding layer (Matsubara, 72, [0032]) is surrounded by a periphery of the dummy element (Haga, left side) as viewed in the thickness direction.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara in view of Ragonese, Schaller, and Haga as applied to claim 10 above, and further in view of Furutani et al. (US PGPub 2020/0388580; herein known as Furutani).
Regarding claim 14, Matsubara in view of Ragonese, Schaller, and Haga teaches the semiconductor device according to claim 10, but does not explicitly teach wherein surface roughness of the second surface is larger than surface roughness of the third surface.
Furutani teaches (Fig. 11) wherein the surface roughness of the second surface (131A, [0208]) is larger than the surface roughness of the third surface (1211A, [0208]).
Because Matsubara in view of Ragonese, Schaller, and Haga and Furutani are directed toward lead frame devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Matsubara in view of Ragonese, Schaller, and Haga and of Furutani to include wherein surface roughness of the second surface is larger than surface roughness of the third surface in order to more reliably suppress formation of cracks in the substrate (Furutani, [0208]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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