DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 18, 2026 has been entered.
Response to Amendment
The amendment filed March 18. 2026 has been entered. Claims 1-11 and 13-15 remain pending in this application. Claim 12 has been cancelled at applicant’s request. Claim 7 has been amended. Claims 14-15 have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,687,452 B1 to Hiroshi Kishibe (hereafter Kishibe) in view of US 7,227,804 B1 to Badrinarayanan Kothandaraman, et al. (hereafter Kothandaraman).
Regarding Claim 1, Kishibe discloses a semiconductor memory device comprising:
a plurality of memory cells (Disclosing memory cells: Kishibe, col.3:66);
a first power supply line (A first power supply line 61: Kishibe, Figure 1) to which a power supply voltage is supplied (VDD supplied to the first supply line: Kishibe, Figure 1);
a second power supply line (A second power supply line 63: Kishibe, Figure 1) serving as a power supply voltage line of the plurality of memory cells (Power supply line providing power to a memory circuit 20: Kishibe, Figure 1);
a first transistor and a second transistor (A first transistor 41 and a second transistor 42: Kishibe, Figure 1)
that are connected in parallel between the first power supply line and the second power supply line (Transistors 41 and 42 connected in parallel between the first and second power supply lines: Kishibe, Figure 1); and
a control circuit (Control circuit 50: Kishibe, Figure 1) that,
in accordance with a first signal for switching between a first mode and a second mode (Control circuit having two modes: Kishibe, col.4:62-63),
the first mode being a mode for supplying the power supply voltage to the plurality of memory cells, the second mode being a mode for not supplying the power supply voltage to the plurality of memory cells (The two modes being on and off: Kishibe, col.4:62-63),
(i) switches off the first transistor and the second transistor in a period of the second mode (During the off mode, the first and second control switches being off: Kishibe, Figure 2) and
(ii) switches on the first transistor when switching from the second mode to the first mode is performed (Control signal switching on the first transistor during transition to the first mode: Kishibe, Figure 2) and
switches on the second transistor after the first transistor is switched on (Switching on the second transistor after the first transistor is switched on: Kishibe, Figure 2).
Kishibe expressly discloses the parallel power supply being provided to the memory peripheral circuits, not specifically the memory cell array itself. Kothandaraman, however, discloses a memory device including transistors arranged in parallel between a first power supply line 210 and a second power supply line 204 wherein the second power supply line supplies power voltage to the plurality of memory cells (Kothandaraman, Figure 2). Kothandaraman teaches this arrangement allows for precise control of power supply (Kothandaraman, col.7:14-20) in a compact arrangement (Kothandaraman, col.3:26-27). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to take the dual switching control circuit of Kishibe and apply it directly to the memory cells as in Kothandaraman, with a reasonable expectation of success. Both inventions are well known in the field of memory circuit power supply and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Kishibe discloses the semiconductor memory device according to claim 1,
wherein the second transistor has a drive performance higher than a drive performance of the first transistor (Disclosing the two transistors having different capacities: Kishibe, col.5:8-14).
Regarding Claim 3, Kishibe discloses the semiconductor memory device according to claim 1, wherein the control circuit includes
a delay circuit that generates a second signal by delaying the first signal (Disclosing a delay circuit that delays the operational control signals: Kishibe, col.6:49-50),
the first signal is supplied to a control terminal of the first transistor (The first signal controlling the first transistor: Kishibe, Figure 2), and
the second signal is supplied to a control terminal of the second transistor (The delayed second signal controlling the second transistor: Kishibe, Figure 2).
Regarding Claim 4, Kishibe discloses the semiconductor memory device according to claim 3, further comprising:
a plurality of memory blocks (Disclosing a plurality of memory blocks 10, 20, and 30: Kishibe, Figure 1) each including the plurality of memory cells (Each memory block including an array of memory cells 12, 22, and 32: Kishibe, Figure 1),
wherein the first transistor and the second transistor are provided in each of the plurality of memory blocks (A power supply circuit 11, 21, and 31 provided within each memory block: Kishibe, Figure 1; Wherein the power supply circuit connected directly to the memory array consists of a plurality of transistors: Kothandaraman, Figure 2), and
the second signal generated by the delay circuit is supplied to the control terminal of each of two or more second transistors (The delayed second signal controlling the second transistor: Kishibe, Figure 2) provided in two or more of the plurality of memory blocks (The control circuit being tied directly to the power supply switches within the memory blocks: Kishibe, Figure 1).
Regarding Independent Claim 13, Kishibe discloses a control method for controlling a semiconductor memory device that includes
a plurality of memory cells (Disclosing memory cells: Kishibe, col.3:66),
a first transistor, and a second transistor (A first transistor 41 and a second transistor 42: Kishibe, Figure 1),
the control method having
a first mode for supplying a power supply voltage to the plurality of memory cells (Control circuit having two modes: Kishibe, col.4:62-63) and
a second mode for not supplying the power supply voltage to the plurality of memory cells (The two modes being on and off: Kishibe, col.4:62-63),
the control method comprising:
supplying the power supply voltage to the plurality of memory cells
via the first transistor during a first period (Control signal switching on the first transistor during transition to the first mode: Kishibe, Figure 2)
after switching from the second mode to the first mode is performed (During the off mode, the first and second control switches being off: Kishibe, Figure 2), and
supplying the power supply voltage to the plurality of memory cells
via the first transistor and the second transistor during a second period after the first period (Switching on the second transistor after the first transistor is switched on: Kishibe, Figure 2).
Kishibe expressly discloses the parallel power supply being provided to the memory peripheral circuits, not specifically the memory cell array itself. Kothandaraman, however, discloses a memory device including transistors arranged in parallel between a first power supply line 210 and a second power supply line 204 wherein the second power supply line supplies power voltage to the plurality of memory cells (Kothandaraman, Figure 2). Kothandaraman teaches this arrangement allows for precise control of power supply (Kothandaraman, col.7:14-20) in a compact arrangement (Kothandaraman, col.3:26-27). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to take the dual switching control circuit of Kishibe and apply it directly to the memory cells as in Kothandaraman, with a reasonable expectation of success. Both inventions are well known in the field of memory circuit power supply and the combination of known inventions with predictable results is obvious and not patentable.
Regarding New Claim 14, Kishibe discloses the semiconductor memory device according to claim 1,
wherein the semiconductor memory device is included in one memory functional block included in an integrated circuit (Showing the memory device as a functional block: Kishibe, Figure 1).
Regarding New Claim 15, Kishibe discloses the semiconductor memory device according to claim 1,
wherein the semiconductor memory device is included in one memory macro included in an integrated circuit (Showing the memory device as an integrated macro: Kishibe, Figure 1; Note: In the absence of an applicant definition, ‘macro’ is understood to be a reusable functional circuit block. Although Kishibe describes some pre-charge circuits within and without a particular macro, see col.6:34-46, this doesn’t preclude the existence of a larger macro encompassing both).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,687,452 B1 to Hiroshi Kishibe (hereafter Kishibe) and US 7,227,804 B1 to Badrinarayanan Kothandaraman, et al. (hereafter Kothandaraman) in view of US 2007/0257727 A1 to Ban Hok Goh (hereafter Goh).
Regarding Claim 5, Kishibe discloses the semiconductor memory device according to claim 1, but fails to explicitly disclose the further limitations of Claim 5. Goh, however, discloses a power supply management circuit as in Claim 1, wherein:
the control circuit detects a voltage of the second power supply line (A control circuit monitoring the voltage at a point: Goh, ¶[0022]), and
after the first transistor is switched on when switching from the second mode to the first mode is performed, and when the voltage of the second power supply line reaches a predetermined voltage, the control circuit switches on the second transistor (Switching on additional transistors once the reference voltage reaches a predetermined level: Goh, ¶[0022]).
Goh teaches this configuration allows for the intelligent sequencing of power supply voltage changes without additional circuits and at set reference voltages after appropriate delays (Goh, ¶0028]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the intelligent voltage monitoring and sequencing of Goh with the dual switching control circuit of Kishibe, with a reasonable expectation of success. Both inventions are well known in the field of power supply management and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,687,452 B1 to Hiroshi Kishibe (hereafter Kishibe) and US 7,227,804 B1 to Badrinarayanan Kothandaraman, et al. (hereafter Kothandaraman) in view of US 2015/0294713 A1 to Robert Charles Beat (hereafter Beat).
Regarding Claim 6, Kishibe discloses a semiconductor memory device as in Claim 1, but does not disclose the further limitations of Claim 6. Beat, however, discloses the semiconductor memory device according to claim 1, further comprising:
wherein the write assist circuit includes the first transistor and the second transistor (The power supply circuit including the first and second transistors: Kishibe, Figure 1), and
one of the first transistor or the second transistor is off during the data writing (Turning off one of the two available transistors would inherently affect the capacity of the circuit).
Kishibe does not disclose a write assist circuit that decreases a voltage of the second power supply line during a data writing operation. Beat, however, discloses a semiconductor memory device as in Claim 1, further comprising
a write assist circuit (A write assist circuit: Beat, Figure 7) that decreases a voltage of the second power supply line (Decreasing the voltage supplied to the memory circuit: Beat, ¶[0044])
to a voltage lower than the voltage of the second power supply line at a time other than during the data writing (Reducing the voltage below what would be otherwise available for other memory operations: Beat, ¶[0044])
during data writing to the plurality of memory cells (Reducing the supply voltage only during writing operations: Beat, ¶[0044]),
Beat teaches lowering the supply voltage to a memory cell assists in ensuring a proper voltage differential across the cell, making it easier to write a ‘1’ to memory (Beat, ¶¶[0043-0044]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the voltage assisted writing operation of Beat with the dual switching control circuit of Kishibe, with a reasonable expectation of success. Both inventions are well known in the field of memory power supply management and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,687,452 B1 to Hiroshi Kishibe (hereafter Kishibe) in view of US 2022/0130455 A1 to Sanjeev Kumar Jain, et al. (hereafter Jain).
Regarding Independent Claim 7, Kishibe discloses a semiconductor memory device comprising:
a plurality of memory cells (Disclosing memory cells: Kishibe, col.3:66);
a first pre-charge circuit and a second pre-charge circuit (A first transistor 41 and a second transistor 42: Kishibe, Figure 1); and
a control circuit that, in accordance with a first signal for switching between a first mode and a second mode,
(i) switches off the first pre-charge circuit and the second pre-charge circuit in a period of the second mode (During the off mode, the first and second control switches being off: Kishibe, Figure 2) and
(ii) switches on the first pre-charge circuit when switching from the second mode to the first mode is performed (Control signal switching on the first transistor during transition to the first mode: Kishibe, Figure 2) and switches on the second pre-charge circuit after the first pre-charge circuit is switched on (Switching on the second transistor after the first transistor is switched on: Kishibe, Figure 2),
the first mode being a mode for pre-charging the first bit line, the second mode being a mode for not pre-charging the first bit line (The two modes being on and off: Kishibe, col.4:62-63).
Kishibe expressly discloses the parallel power supply being provided to the memory peripheral circuits, not specifically the memory cell array itself. By extension, Kishibe does not disclose the first and second pre-charge circuits being connected to first and second bit lines, nor a circuit where the first pre-charge circuit includes: a first transistor that includes a source and a drain, one of which is connected to the first bit line, and a gate to which the first signal is to be supplied; and a second transistor that includes a source and a drain, one of which is connected to the second bit line, and a gate to which the first signal is to be supplied, the second pre-charge circuit includes: a third transistor that includes a source and a drain, one of which is connected to the first bit line, and a gate to which a second signal is to be supplied; and a fourth transistor that includes a source and a drain, one of which is connected to the second bit line, and a gate to which the second signal is to be supplied, in the period of the second mode, the first transistor, the second transistor, the third transistor, and the fourth transistor are switched off based on the first signal and the second signal, and when the switching from the second mode to the first mode is performed,(i) the first transistor and the second transistor are switched on, and(ii) the third transistor and the fourth transistor are switched on after the first transistor and the second transistor are switched on, wherein (i) and (ii) are performed based on the first signal and the second signal.
Jain, however, discloses a pre-charge control circuit wherein:
a first bit line and a second bit line that are connected to the plurality of memory cells (First and second bitlines BL and BLB connected to a plurality of memory cells: Jain, ¶[0022]);
a first pre-charge circuit and a second pre-charge circuit that are connected to the first bit line and the second bit line (First and second pre-charge circuits connected to the first and second bit lines: Jain, ¶[0025]); and
the first pre-charge circuit includes:
a first transistor that includes a source and a drain (Transistors: Jain, ¶[0027]),
one of which is connected to the first bit line (Transistors connected to first and second bit lines: Jain, ¶[0027]), and
a gate to which the first signal is to be supplied (Transistor gate controlled by the sleep signal: Jain, ¶[0027]); and
a second transistor that includes a source and a drain (Transistors: Jain, ¶[0027]),
one of which is connected to the second bit line (Transistors connected to first and second bit lines: Jain, ¶[0027]), and
a gate to which the first signal is to be supplied (Transistor gate controlled by the sleep signal: Jain, ¶[0027]),
the second pre-charge circuit includes:
a third transistor that includes a source and a drain (Second pre-charge circuit transistors: Jain, ¶[0029]), one of which is connected to the first bit line (Transistors connected to first and second bit lines: Jain, ¶[0029]), and a gate to which a second signal is to be supplied (Transistor gate controlled by the sleep signal: Jain, ¶[0029]); and
a fourth transistor that includes a source and a drain (Second pre-charge circuit transistors: Jain, ¶[0029]), one of which is connected to the second bit line (Transistors connected to first and second bit lines: Jain, ¶[0029]), and a gate to which the second signal is to be supplied (Transistor gate controlled by the sleep signal: Jain, ¶[0029]),
in the period of the second mode, the first transistor, the second transistor, the third transistor, and the fourth transistor are switched off based on the first signal and the second signal (The first through fourth transistors controlled by the first and second signal: Jain, ¶¶[0027 & 0029]; Note: In circuitry, a transistor being switched on or off by the control signal is routinely substituted one for the other with predictable results), and
when the switching from the second mode to the first mode is performed,
(i) the first transistor and the second transistor are switched on (The first and second transistors being controlled by the first signal: Jain, ¶[0027]), and
(ii) the third transistor and the fourth transistor are switched on after the first transistor and the second transistor are switched on (The third and fourth transistors being controlled by a second signal after a delay: Jain, ¶[0029]),
wherein (i) and (ii) are performed based on the first signal and the second signal (The first through fourth transistors controlled by the first and second signal: Jain, ¶¶[0027 & 0029]).
Jain teaches controlled pre-charging of bit lines is necessary, otherwise the circuits may suffer from a large in-rush current, which may cause component failure and excess power draw in constrained devices (Jain, ¶[0017]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to apply the staged pre-charge architecture described in Kishibe to the memory cell bit line pre-charge method of Jain, with a reasonable expectation of success. Both inventions are well known in the art of memory array pre-charge circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 8, Kishibe discloses the semiconductor memory device according to claim 7,
wherein the second transistor has a drive performance higher than a drive performance of the first transistor (Disclosing the two transistors having different capacities: Kishibe, col.5:8-14).
Regarding Claim 9, Kishibe discloses the semiconductor memory device according to claim 7, wherein the control circuit includes
a delay circuit that generates a second signal by delaying the first signal (Disclosing a delay circuit that delays the operational control signals: Kishibe, col.6:49-50),
the first signal is supplied to a control terminal of the first transistor (The first signal controlling the first transistor: Kishibe, Figure 2), and
the second signal is supplied to a control terminal of the second transistor (The delayed second signal controlling the second transistor: Kishibe, Figure 2).
Regarding Claim 10, Kishibe discloses the semiconductor memory device according to claim 9, further comprising:
a plurality of memory blocks (Disclosing a plurality of memory blocks 10, 20, and 30: Kishibe, Figure 1) each including the plurality of memory cells (Each memory block including an array of memory cells 12, 22, and 32: Kishibe, Figure 1),
wherein the first transistor and the second transistor are provided in each of the plurality of memory blocks (A power supply circuit 11, 21, and 31, inherently consisting of transistors, provided within each memory block: Kishibe, Figure 1), and
the second signal generated by the delay circuit is supplied to the control terminal of each of two or more second transistors (The delayed second signal controlling the second transistor: Kishibe, Figure 2) provided in two or more of the plurality of memory blocks (The control circuit being tied directly to the power supply switches within the memory blocks: Kishibe, Figure 1).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,687,452 B1 to Hiroshi Kishibe (hereafter Kishibe) and US 2022/0130455 A1 to Sanjeev Kumar Jain, et al. (hereafter Jain) in view of US 2007/0257727 A1 to Ban Hok Goh (hereafter Goh).
Regarding Claim Claim 11, Kishibe discloses the semiconductor memory device according to claim 7, but fails to explicitly disclose the further limitations of Claim 5. Goh, however, discloses a power supply management circuit as in Claim 1, wherein:
the control circuit detects a voltage of the second power supply line (A control circuit monitoring the voltage at a point: Goh, ¶[0022]), and
after the first transistor is switched on when switching from the second mode to the first mode is performed, and when the voltage of the second power supply line reaches a predetermined voltage, the control circuit switches on the second transistor (Switching on additional transistors once the reference voltage reaches a predetermined level: Goh, ¶[0022]).
Goh teaches this configuration allows for the intelligent sequencing of power supply voltage changes without additional circuits and at set reference voltages after appropriate delays (Goh, ¶0028]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the intelligent voltage monitoring and sequencing of Goh with the dual switching control circuit of Kishibe, with a reasonable expectation of success. Both inventions are well known in the field of power supply management and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed March 18, 2026 have been fully considered but they are not persuasive.
Applicant argues neither Kishibe nor Kothandaraman discloses a control circuit switching the several transistors on or off depending on the present circuit mode and timing requirements, in accordance with a first signal (Applicant Arguments/Remarks, Page 6, ¶4). Kishibe clearly discloses managing the power supply being made available to the circuit (See, for instance, Kishibe, col.6:3-33). This level of control inherently requires a controller. Said controller may be as simple as a single transistor or a delay circuit, provided as it meets the power and timing requirements. Applicant further argues there is no reasonable reason to combine the Kothandaraman and Kishibe, specifically because Kishibe seeks to reduce the inrush current in the peripheral circuitry of a memory device while Kothandaraman seeks to manage a standby current and not an inrush current (Applicant Arguments/Remarks, page 8 ¶3). Taking these points in turn, as stated in previous office actions, Kishibe anticipates the increasing power requirements as circuit sizes increase (Kishibe, col.2:13-17). Applicant states this line continues to refer only to peripheral circuits, although that argument is unpersuasive. Kishibe is primarily focused on managing the inrush current of peripheral circuits, it makes no sense to further condition that management on circuit size. Kishibe does state the disclosed inrush current management circuits are not necessary for memory cells (Kishibe, col.5:57-63), but in light of the preceding statement it is clear this only remains true as long as the parasitic capacitance remains small. Further, the present invention is not limited to only controlling the inrush current associated with the memory cells – except for Claim 7, amended, which is addressed separately – but may also apply to the peripheral circuits (Specification, page 11 lines 10-12). Therefore, prior art specifically drawn to controlling the inrush current of memory device peripheral circuits is germane.
Applicant argues Kothandaraman pertains to managing a standby current and not specifically an inrush current (Applicant Arguments/Remarks, page 8 ¶3). This is merely a matter of labeling. Kothandaraman discloses a method for managing current flows through activation of a transistor network, it is irrelevant for the purposes of examination how that current is labeled; broadest reasonable interpretation requires a more expansive reading.
Finally, in regards to amended Claim 7, Applicant argues the amended claim differs from the previously cited prior art because, “the power supply to the pre-charge circuit is not switched ON/OFF, instead the pre-charge circuit itself is switched ON/OFF” (Applicant Arguments/Remarks, page 9 ¶7). This argument draws an arbitrary distinction. Any electrical circuit is inherently concerned with managing power. Whether the power supply is controlled internal or external to the circuit is only a question of where the line is drawn separating the interior from the exterior.
Applicant’s remaining arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7,499,310 B2 to Chul-Sung Park, et al.: Disclosing cross connected bit line voltage switches.
US 7,751,267 B2 to Rajiv V. Joshi, et al.: Disclosing a set of cross-connected transistors managing parallel bit line voltages.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
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