Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 21, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 18 recites the limitation "the conductive post" in lines 3 and 6. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, the examiner interprets “the conductive post” as “a conductive post” However, appropriate correction and/or clarification is requested. Claim 20 recites the limitation "the second semiconductor substrate" in line 3. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, the examiner interprets “the second semiconductor substrate” as “a second semiconductor substrate” However, appropriate correction and/or clarification is requested.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (Pub. No. : US 2020/0006324 A1).
Regarding Claim 20, Chen et al. discloses a semiconductor package, comprising: a redistribution substrate (Par. 0045; Fig. 6 – redistribution layer structure 402 could be considered as the redistribution substrate); a first semiconductor chip and a dummy chip disposed on the redistribution substrate and spaced apart from each other (Par. 0045-0055; Fig. 6 – first semiconductor chip 200; dummy chip 300); a second semiconductor chip covering both the first semiconductor chip and the dummy chip (Par. 0045-0055; Fig. 6 – second semiconductor chip 100; covering the back surface of the first semiconductor chip 200 and the dummy chip 300); a mold layer filling a space between the redistribution substrate and the second semiconductor chip (Par. 0045-0055; Fig. 6 – mold layer DE); and a conductive post vertically penetrating the mold layer and connecting the redistribution substrate to the second semiconductor chip (Par. 0045-0055; Fig. 6 – conductive post comprising TDV), wherein the first semiconductor chip comprises: a first semiconductor substrate, including an integrated circuit formed on a top surface thereof facing the second semiconductor chip (Par. 0045-0055; Fig. 6 – first semiconductor substrate S2); and a first circuit layer disposed on the top surface of the first semiconductor substrate and electrically connected to the integrated circuit (Par. 0045-0055; Fig. 6), wherein the dummy chip comprises: the second semiconductor substrate (Par. 0045-0055; Fig. 6 – second semiconductor substrate S3); a second circuit layer disposed on a top surface of the second semiconductor substrate (Par. 0045-0055; Fig. 6); and first vias vertically penetrating the second semiconductor substrate and connected to the second circuit layer, the first vias comprising protruding portions extended to a region below a bottom surface of the second semiconductor substrate (Par. 0045-0055; Fig. 6 – first vias TSVb), wherein a width of the first vias is substantially equal to or larger than a width of the conductive post (Par. 0054; Fig. 6 – this prior art teaches “In some embodiments, a dimension of the through dielectric vias TDV is different from a dimension of the through substrate vias TSVa or TSVb”; this statement leaves all options related to the widths of the various vias with respect to the widths of the other vias a possibility).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 and 11 are rejected under 35 U.S.C. 103 as obvious over Tsai et al. (Pub. No.: US 2023/0154913 A1) in view of Chen et al. (Pub. No. : US 2020/0006324 A1) and Kim et al. (Pub. No. : US 2023/0065378 A1).
Regarding Claim 1, Tsai et al. discloses a semiconductor package, comprising: a first semiconductor chip (Par. 0054-0062; Figs. 23-34 – first semiconductor chip 30); a second semiconductor chip disposed on an active surface of the first semiconductor chip (Par. 0054-0062; Figs. 23-34 – second semiconductor chip 50A); a dummy chip disposed on the active surface of the first semiconductor chip and horizontally spaced apart from the second semiconductor chip (Par. 0054-0062; Figs. 23-34 – dummy chip 55); a mold layer disposed on the active surface of the first semiconductor chip and enclosing both the second semiconductor chip and the dummy chip (Par. 0054-0062; Figs. 23-34 –mold layer 61); and wherein an active surface of the second semiconductor chip and an active surface of the dummy chip are each in direct contact with the active surface of the first semiconductor chip (Par. 0054-0062; Figs. 23-34), wherein the dummy chip comprises a first via vertically penetrating the dummy chip, the first via being exposed to a region on a top surface of the dummy chip (Par. 0054-0062; Figs. 23-34 – dummy chip 55; first via 55v), wherein the second semiconductor chip comprises a second via vertically penetrating the second semiconductor chip, the second via being exposed to a region on a top surface of the second semiconductor chip (Par. 0047, 0054-0062; Figs. 23-34 – second semiconductor chip 50A; second via 52), and wherein a first width of the first via is larger than a second width of the second via (Figs. 25-34).
Tsai et al. does not explicitly disclose a conductive post vertically penetrating the mold layer proximate to the second semiconductor chip and the dummy chip coupled to the active surface of the first semiconductor chip. However, Chen et al., at least implicitly teaches a conductive post vertically penetrating the mold layer proximate to the second semiconductor chip and the dummy chip coupled to the active surface of the first semiconductor chip (Par. 0045; Fig. 6 – conductive post comprising TSV; second semiconductor chip 200; dummy chip 300; first semiconductor chip 100). Furthermore, Kim et al., at least implicitly teaches a conductive post vertically penetrating the mold layer proximate to the second semiconductor chip coupled to the active surface of the first semiconductor chip (Par. 0027; Figs. 1A-1B – conductive post 312). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Chen et al. and Kim et al. to adapt a semiconductor package, comprising:: a conductive post vertically penetrating the mold layer proximate to the second semiconductor chip and the dummy chip of Tsai et al. coupled to the active surface of the first semiconductor chip s in order to implement a package with complex functionalities
Regarding Claim 2, modified Tsai et al., as applied to claim 1, discloses the semiconductor package, wherein a third width of the conductive post is larger than the second width of the second via (Kim et al.- Figs. 1A-1B – conductive post 312; second via 215).
Regarding Claim 3, modified Tsai et al., as applied to claim 2, discloses the semiconductor package, wherein the third width of the conductive post is substantially equal to the first width of the first via (Tsai et al.- Par. 0024; Figs. 13 and 28 – an indirect comparison seems to suggest that the third width of the conductive post 66 and first width of the first via 55v have similar widths).
Regarding Claim 4, modified Tsai et al., as applied to claim 1, discloses the semiconductor package, wherein the first width of the first via is 5 to 50 times larger than the second width of the second via (Tsai et al.- Par. 0024, 0065; Fig. 33 - second width of the second via may be between 2 µm to 7 µm; the width of the conductive post is greater than 15 µm; the dummy chip has a functionality similar to the conductive post as far as internal resistance is concerned; assuming the second vias have similar widths to the widths of the conductive post, under certain embodiments, at least, the first width of the first vias will be more than 5 times larger than the second width of the second via)
Regarding Claim 5, modified Tsai et al., as applied to claim 4, discloses the semiconductor package, wherein the first width of the first via ranges from 10 µm to 100 µm, and wherein the second width of the second via ranges from 0.2 µm to 2 µm (Tsai et al.- Par. 0024, 0065; Fig. 33 - this prior art teaches that the second width of the second via may be between 2 µm to 7 µm; the width of the conductive post is greater than 15 µm; the dummy chip has a functionality similar to the conductive post as far as internal resistance is concerned; it can be assumed that the first width of the first via is larger than 15 µm; the width of the second via is dictated by the densely packed circuitries in the second semiconductor chip which generally requires very narrow vias to house all the metal traces and the vias and trenches in a small space; the width of the first via is intentionally made much larger, on the other hand, to reduce heat dissipation through vias which carries large currents; it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955)).
Regarding Claim 6, modified Tsai et al., as applied to claim 1, discloses the semiconductor package, wherein the first via comprises a protruding portion extended to a region on the top surface of the dummy chip, and wherein the second via comprises a protruding portion extended to a region on the top surface of the second semiconductor chip (Tsai et al.- Figs. 32-34)
Regarding Claim 7, modified Tsai et al., as applied to claim 6, discloses the semiconductor package, wherein the mold layer covers both the top surface of the dummy chip and the top surface of the second semiconductor chip, and wherein the first via and the second via are exposed to a region on a top surface of the mold layer (Tsai et al.- Figs. 32-34)
Regarding Claim 8, modified Tsai et al., as applied to claim 1, discloses the semiconductor package, further comprising: a redistribution substrate disposed on the mold layer; and outer terminals disposed on a top surface of the redistribution substrate, wherein the first via, the second via, and the conductive post are each coupled to the redistribution substrate (Tsai et al.- Par. 0037, 0064; Figs. 32-34 – redistribution substrate 200; outer terminal 220)
Regarding Claim 11, modified Tsai et al., as applied to claim 1, discloses the semiconductor package, wherein, at an interface between the first semiconductor chip and the second semiconductor chip, first chip pads of the first semiconductor chip and second chip pads of the second semiconductor chip are in direct contact with each other and form a single object, and wherein at an interface between the first semiconductor chip and the dummy chip, third chip pads of the first semiconductor chip and fourth chip pads of the dummy chip are in contact with each other and form a single object. (Tsai et al.- Figs. 32-34)
Claim 9 is rejected under 35 U.S.C. 103 as obvious over Tsai et al. (Pub. No.: US 2023/0154913 A1), Chen et al. (Pub. No. : US 2020/0006324 A1) and Kim et al. (Pub. No. : US 2023/0065378 A1), as applied to claim 8.
Regarding Claim 9, modified Chen et al., as applied to claim 8, discloses the semiconductor package, wherein the first semiconductor chip is electrically connected to the redistribution substrate through the first via of the dummy chip and the conductive post (Chen et al. - Par. 0045-0055; Fig. 6).
Modified Chen et al. does not explicitly disclose wherein the dummy chip is configured to deliver an operation signal of the first semiconductor chip, and wherein the conductive post is configured to deliver a power/ground signal of the first semiconductor chip.
However, it would be obvious to use wider vias to push large currents through it in order to reduce heat generation. In that sense, both the conductive post and the dummy chip are suitable for delivering both the power/ground signal and the operation signal to the second semiconductor chip.
Modified Chen discloses the claimed invention except for the semiconductor package, wherein the dummy chip is configured to deliver an operation signal of the first semiconductor chip, and wherein the conductive post is configured to deliver a power/ground signal of the first semiconductor chip., It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein the dummy chip is configured to deliver an operation signal of the first semiconductor chip, and wherein the conductive post is configured to deliver a power/ground signal of the first semiconductor chip, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Claims 12-15 and 19 are rejected under 35 U.S.C. 103 as obvious over Chen et al. (Pub. No. : US 2020/0006324 A1) in view of Tsai et al. (Pub. No.: US 2023/0154913 A1).
Regarding Claim 12, Chen et al. discloses a semiconductor package, comprising: a redistribution substrate (Par. 0045; Fig. 6 – redistribution layer structure 402 could be considered as the redistribution substrate); a first semiconductor chip disposed on the redistribution substrate (Par. 0045-0055; Fig. 6 – first semiconductor chip 200); a dummy chip disposed on the redistribution substrate and horizontally spaced apart from the first semiconductor chip (Par. 0045-0055; Fig. 6 – first semiconductor chip 200; dummy chip 300); a second semiconductor chip disposed on both the first semiconductor chip and the dummy chip (Par. 0045-0055; Fig. 6 – second semiconductor chip 100; covering the back surface of the first semiconductor chip 200 and the dummy chip 300); a mold layer filling a space between the redistribution substrate and the second semiconductor chip (Par. 0045-0055; Fig. 6 – mold layer DE); and outer terminals disposed on a bottom surface of the redistribution substrate (Par. 0041-0042; Fig. 6), wherein the first semiconductor chip comprises: a first semiconductor substrate (Par. 0045-0055; Fig. 6 – first semiconductor substrate S2); a first circuit layer disposed on the first semiconductor substrate (Par. 0045-0055; Fig. 6); first pads disposed on a top surface of the first circuit layer (Par. 0045-0055; Fig. 6); and first vias vertically penetrating the first semiconductor substrate and coupled to the first circuit layer (Par. 0045-0055; Fig. 6 first vias TSVa), wherein the dummy chip comprises: a second semiconductor substrate (Par. 0045-0055; Fig. 6 – second semiconductor substrate S3); second pads disposed on the second semiconductor substrate (Par. 0045-0055; Fig. 6); and second vias vertically penetrating the second semiconductor substrate and electrically connected to the second pads (Par. 0045-0055; Fig. 6 – first vias TSVb), wherein the first pads and the second pads are in contact with third pads of the second semiconductor chip (Par. 0045-0055; Fig. 6). Chen et al. does not explicitly disclose wherein a width of the second vias is 5 to 50 times larger than a width of the first vias.
However Tsai et al., at least implicitly teaches wherein a width of the second vias is 5 to 50 times larger than a width of the first vias (Par. 0024, 0065; Figs. 32-34 - first via 52; second via 55v; first width of the first via may be between 2 µm to 7 µm; the width of the conductive post is greater than 15 µm; the dummy chip 55 of Figs. 32-34 has a functionality similar to the conductive post 66A of Figs. 9-15 as far as internal resistance is concerned; assuming the second vias have similar widths to the widths of the conductive post, under certain embodiments, at least, the second width of the second vias will be more than 5 times larger than the first width of the first via). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Tsai et al. to adapt a semiconductor package, comprising: wherein a width of the second vias of Chen et al. is 5 to 50 times larger than a width of the first vias in order to reduce internal resistance which improves the overall device performance as taught by Tsai et al. (Par. 0013).
Regarding Claim 13, modified Chen et al., as applied to claim 12, discloses the semiconductor package, further comprising a conductive post vertically penetrating the mold layer and connecting the redistribution substrate to the second semiconductor chip (Chen et al. - Par. 0045-0055; Fig. 6 – conductive post comprising TDV), wherein a width of the conductive post is larger than the width of the first vias (Tsai et al. - Par. 0024, 0065; Figs. 9-15 together with 32-34; see rejection of claim 12 above – conductive post 66A has a width larger than a width of the first via 52; by making the conductive post width large internal resistance could be reduced and device performance improved).
Regarding Claim 14, modified Chen et al., as applied to claim 13, discloses the semiconductor package, wherein the width of the conductive post is substantially equal to the width of the second vias (please see the rejection of claim 12 above).
Regarding Claim 15, modified Chen et al., as applied to claim 12, discloses the semiconductor package, wherein the width of the second vias ranges from 10 µm to 100 µm, and wherein the width of the first vias ranges from 0.2 µm to 2 µm ((Tsai et al.- Par. 0024, 0065; Fig. 33 - this prior art teaches that the width of the first via may be between 2 µm to 7 µm; the width of the conductive post is greater than 15 µm; the dummy chip has a functionality similar to the conductive post as far as internal resistance is concerned; it can be assumed that the first width of the first via is larger than 15 µm; the width of the first via is dictated by the densely packed circuitries in the first semiconductor chip which generally requires very narrow vias to house all the metal traces and the vias and trenches in a small space; the width of the second via is intentionally made much larger, on the other hand, to reduce heat dissipation through vias which carries large currents; it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955)).
Regarding Claim 19, modified Chen et al., as applied to claim 12, discloses the semiconductor package, wherein at an interface between the first semiconductor chip and the second semiconductor chip, the first pads and the third pads are in direct contact with each other and form a single object (Chen et al. - Par. 0045-0055; Fig. 6), and wherein at an interface between the second semiconductor chip and the dummy chip, the second pads and the third chip pads are in contact with each other and form a single object (Chen et al. - Par. 0045-0055; Fig. 6),
Claim 18 is rejected under 35 U.S.C. 103 as obvious over Chen et al. (Pub. No. : US 2020/0006324 A1) and Tsai et al. (Pub. No.: US 2023/0154913 A1), as applied to claim 12.
Regarding Claim 18, modified Chen et al., as applied to claim 12, discloses the semiconductor package, wherein the second semiconductor chip is electrically connected to the redistribution substrate through the second vias of the dummy chip and the conductive post (Chen et al. - Par. 0045-0055; Fig. 6).
Modified Chen et al. does not explicitly disclose wherein the dummy chip is configured to deliver an operation signal of the second semiconductor chip, and wherein the conductive post is configured to deliver a power/ground signal of the second semiconductor chip,
However, it would be obvious to use wider vias to push large currents through it in order to reduce heat generation. In that sense, both the conductive post and the dummy chip are suitable for delivering both the power/ground signal and the operation signal to the second semiconductor chip.
Modified Chen discloses the claimed invention except for the semiconductor package, wherein the dummy chip is configured to deliver an operation signal of the second semiconductor chip, and wherein the conductive post is configured to deliver a power/ground signal of the second semiconductor chip, It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor package, wherein the dummy chip is configured to deliver an operation signal of the second semiconductor chip, and wherein the conductive post is configured to deliver a power/ground signal of the second semiconductor chip, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Allowable Subject Matter
Claims 10, 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure
1. Marimuthu et al. (Patent No.: US 7838337 B2 – This prior art teaches a semiconductor package, comprising: a first semiconductor chip (chip of package 134); a second semiconductor chip (102) disposed on an active surface of the first semiconductor chip; a dummy chip (104 & 106) disposed on the active surface of the first semiconductor chip and horizontally spaced apart from the second semiconductor chip; a mold layer (118) disposed on the active surface of the first semiconductor chip and enclosing both the second semiconductor chip and the dummy chip; and 114) vertically penetrating the dummy chip, the first via being exposed to a region on a top surface of the dummy chip, wherein
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07/11/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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