DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim of priority to Italian application IT102023000011085, filed May 31, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 21, 2024 is being considered by the examiner.
Claim Objections
Claim 11 is objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim should refer to other claims in the alternative only. See MPEP § 608.01(n). It is further unclear what “when dependent on claim 8” means. Accordingly, claim 11 has not been further treated on the merits.
Specification
The disclosure is objected to because of the following informalities:
Para. [0023] uses the symbol “÷” to denote a range. The Examiner understands that although this is common in Italian documents such as the application to which the instant application claims foreign priority, the use of the symbol for that purpose is not standard in English. The Examiner recommends changing the symbol to a dash to avoid confusion.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 10, 12-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mizan-623 (US 2019/0081623 A1).
With respect to claim 1, Mizan-623 teaches in Fig. 7:
A heterojunction power device (GaN power transistor 200), comprising: a substrate including a semiconductor material (this topology may be used to form large area lateral GaN power transistors, such as GaN E-mode HEMTs, fabricated on a silicon substrate);
a first active area (see annotated Fig. 7 below) and a second active area (see annotated Fig. 7), arranged on the substrate symmetrically opposite with respect to an axis of symmetry and accommodating respective heterostructures;
a separation region (see annotated Fig. 7), extending along the axis of symmetry between the first active area and the second active area;
a first conductive bus (gate bus 216) configured to distribute a first electric potential of the power device in parallel to the first and the second active areas (para. 65 “the gate electrodes of each transistor island are interconnected in parallel by a gate bus 216”);
and a second conductive bus (source bus 212) configured to distribute a second electric potential of the power device, different from the first electric potential, in parallel to the first and the second active areas (para. 65 “The source electrodes of each transistor island are interconnected in parallel by a source bus 212,”)
wherein the first and the second conductive buses extend along the axis of symmetry above the separation region (see Fig. 7, a portion of 212 and 216 runs along the axis of symmetry),
the second conductive bus (212 within second layer of on-chip conductive metallization M2) overlying the first conductive bus (216 within first layer of on-chip conductive metallization M1)).
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With respect to claim 2, Mizan-623 further teaches:
wherein the first conductive bus is a gate bus (gate bus 216) and the first electric potential is a control signal of the power device.
With respect to claim 3, Mizan-623 further teaches:
wherein the second conductive bus is a source bus (source bus 212) and the second electric potential is a source electric potential of the power device.
With respect to claim 10, the Examiner takes Official Notice that one of ordinary skill in the art would understand that the recitation of “GaN E-mode HEMT” of para. [0031] of Mazin-623 implicitly recites a structure of a barrier layer and channel layer heterojunctions. Therefore, Mazin-623 teaches:
wherein the first and the second active areas each include: a respective channel layer and a respective barrier layer defining respective heterojunctions (implicit to a GaN E-mode HEMT device);
a plurality of respective active elements (transistor elements 420 in Fig. 10), extending transversely to the axis of symmetry and arranged periodically along the axis of symmetry,
wherein the active elements include respective portions of the channel layers and of the barrier layers and respective gate regions superimposed, in contact, on the barrier layer of the respective active area (implicit to GaN E-mode HEMT);
the active elements each further including a drain terminal, a source terminal and a gate terminal (para. 71 “transistor elements 420 comprise source electrode fingers S and drain electrode fingers D, with gate electrode fingers extending over the channel region between each S/D electrode pair”);
and the gate terminals including gate electrodes, superimposed, in contact, on respective gate regions and extending transversely to the axis of symmetry.
With respect to claim 12, Mizan-623 further teaches:
wherein the first conductive bus, the gate electrodes and the gate terminals are all electrically connected to each other in a direct manner (para. 65 “the gate electrodes of each transistor island are interconnected in parallel by a gate bus 216.”)
With respect to claim 13, Mizan-623 further teaches:
wherein the active elements are HEMT-type transistors, electrically connected to each other in parallel and formed in gallium nitride technology (para. 65 “The source electrodes of each transistor island are interconnected in parallel by a source bus 212; the drain electrodes of each transistor island are interconnected in parallel by a drain bus 214; and the gate electrodes of each transistor island are interconnected in parallel by a gate bus 216”, para. 31 “GaN E-mode HEMTs”).
With respect to claim 14, Mizan-623 teaches:
A process for manufacturing a heterojunction power device, comprising:
on a substrate including semiconductor material (para. 31 “this topology may be used to form large area lateral GaN power transistors, such as GaN E-mode HEMTs, fabricated on a silicon substrate”),
forming a first active area (see annotated Fig. 7) and a second active area (see annotated Fig. 7) symmetrically opposite with respect to an axis of symmetry, accommodating respective heterostructures (transistors on transistor islands) and separated by a separation region (see annotated Fig. 7), extending along the axis of symmetry;
forming, on the separation region, a first conductive bus (gate bus 216) configured to distribute a first electric potential of the power device in parallel to the first and the second active areas (para. 65 “the gate electrodes of each transistor island are interconnected in parallel by a gate bus 216”);
and forming, on the separation region, a second conductive bus (source bus 212) configured to distribute a second electric potential of the power device, different from the first electric potential, in parallel to the first and the second active areas (para. 65 “The source electrodes of each transistor island are interconnected in parallel by a source bus 212,”),
wherein the first and the second conductive buses extend along the axis of symmetry the second conductive bus overlying the first conductive bus (212 overlies 216 as shown in Fig. 7).
With respect to claim 16, Mizan-623 teaches:
A method comprising: distributing a first electric potential (gate potential) from a first conductive bus (gate bus 216) in parallel to first transistor terminals of first active area (see annotated Fig. 7) and to first transistor terminals of a second active area (see annotated Fig. 7) (para. 65 “the gate electrodes of each transistor island are interconnected in parallel by a gate bus 216”),
the first active area and a second active area arranged on the semiconductor substrate (para. 31 “this topology may be used to form large area lateral GaN power transistors, such as GaN E-mode HEMTs, fabricated on a silicon substrate”) symmetrically opposite with respect to an axis of symmetry and accommodating respective heterostructures (GaN devices),
the first conductive bus being positioned on a separation region extending along the axis of symmetry between the first active area and the second active area (conductive buses 212 and 216 both run along the axis of symmetry);
and distributing a second electric potential (source potential) from a second conductive bus in parallel (source bus 212) to second transistor terminals (source terminals) of the first and the second active areas,
wherein the first and the second conductive buses are stacked and extend along the axis of symmetry above the separation region (212 is stacked above 216 as shown in Fig. 7).
With respect to claim 17, Mizan-623 further teaches:
wherein the first transistor terminals are gate terminals, wherein the first conductive bus is a gate bus (gate bus 216) and the first electric potential is a control signal of the power device (para. 65 “the gate electrodes of each transistor island are interconnected in parallel by a gate bus 216”).
With respect to claim 18, Mizan-623 further teaches:
wherein the second transistor terminals are source terminals, wherein the second conductive bus is a source bus (source bus 212) and the second electric potential is a source electric potential (para. 65 “The source electrodes of each transistor island are interconnected in parallel by a source bus 212,”).
With respect to claim 19, Mizan-623 further teaches:
wherein the first conductive bus and the gate terminals are all electrically connected to each other in a direct manner (para. 65 “the gate electrodes of each transistor island are interconnected in parallel by a gate bus 216”).
With respect to claim 20, Mizan-623 further teaches:
wherein the first and second transistor terminals are terminals of HEMT-type transistors electrically connected to each other in parallel and formed in gallium nitride technology (para. 31 “this topology may be used to form large area lateral GaN power transistors, such as GaN E-mode HEMTs, fabricated on a silicon substrate”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mizan-623 (US 2019/0081623 A1) as applied to claims 1 and 14 above and further in view of Mizan-141 (US 2019/0081141 A1).
With respect to claim 4, Mizan-623 teaches all limitations of independent claim 1 upon which claim 4 depends. Mizan-623 further teaches:
comprising a first level of metallization (first metallization layer M1), wherein the first conductive bus is a portion of the first level of metallization (para. 66 “the conductive tracks of the gate bus are formed from a first layer of on-chip conductive metallization (M1)”);
Mizan-623 fails to teach:
the first level of metallization further including: first-level drain electrodes and first-level source electrodes associated with the first active area, extending transversely to the first conductive bus and superimposed on the first active area; and first-level drain electrodes and first-level source electrodes associated with the second active area, extending transversely to the first conductive bus, superimposed on the second active area and separated, at the separation region, from the first-level drain electrodes and from the first-level source electrodes associated with the first active area.
Mizan-141 teaches in Fig. 8:
the first level of metallization (metallization layer M1) further including: first-level drain electrodes (drain finger electrodes 706) and first-level source electrodes (source finger electrodes 704) associated with the first active area (“active-area”), extending transversely to the first conductive bus (gate bus 719) and superimposed on the first active area (“active area”);
and first-level drain electrodes (706) and first-level source electrodes (704) associated with the second active area (Fig. 8 shows only one cell or section of a multi-section transistor. The layout with multiple cells may be seen for example in Fig. 5, with first active region 402(i) and second active region 402(i+1)), extending transversely to the first conductive bus (719),
superimposed on the second active area and separated, at the separation region (portion covered by the gate and source busses), from the first-level drain electrodes (706 within first region) and from the first-level source electrodes (704 within first region) associated with the first active area.
Mizan-623 discloses the claimed invention except for the limitations regarding what level of metallization the source and drain electrodes are formed on. Mizan-141 teaches that it is known to form source and drain metallization in the first layer and second layer with the relationship to the bus as claimed. It would be obvious to one of ordinary skill in the art to modify Mizan-623 by Mizan-141 to make source and drain fingers extending transverse to the gate bus in the first metallization layer for the purpose of optimizing current density within the electrodes (abstract). See MPEP 2144.
With respect to claim 5, Mizan-141 further teaches:
wherein the first-level drain electrodes and the first-level source electrodes associated with the first active area are arranged in a symmetrical manner, with respect to the axis of symmetry, to respective first-level drain electrodes and first-level source electrodes associated with the second active area (Fig. 5 shows how individual cells are lain out which may be applied to the embodiment of Fig. 8 in which the source and drain fingers are arranged symmetrically about the central gate bus);
and wherein in the first active area and in the second active area the first-level drain electrodes are arranged alternating, along the axis of symmetry, with the first-level source electrodes (see Fig. 8, source and drain fingers alternate).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Mizan-623 in view of Mizan-141 as explained above.
With respect to claim 6, Mizan-623 further teaches:
comprising a second level of metallization (metallization layer M2) superimposed on the first level of metallization (M1),
wherein the second conductive bus (212) is a portion of the second level of metallization (see Fig. 7);
Mizan-141 teaches in para. [0038] that the source and drain finger electrodes may be made of multiple metal layers. Defining the second layer of the source and drain finger electrodes as being within the second metallization layer teaches:
the second level of metallization further including:
second-level drain electrodes (second layer of 706 within first active area) and second-level source electrodes (second layer of 704 within first active area) associated with the first active area,
extending transversely to the second conductive bus and superimposed on the first active area (704 and 706 extend toward 724);
second-level drain electrodes (second layer of 706 within second active area) and second-level source electrodes (second layer of 704 within second active area) associated with the second active area,
extending transversely to the second conductive bus and superimposed on the second active area (704 and 706 extend toward 724);
the second-level source electrodes extending from the second conductive bus (724) in opposite directions with respect to the axis of symmetry (line that extends along the center of 719);
and the second-level drain electrodes associated with the first active area being separated, at the separation region, from the second-level drain electrodes associated with the second active area (706 in first active region and second active region are separated from each other by the busses).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Mizan-623 in view of Mizan-141 as explained above.
With respect to claim 7, Mizan-141 further teaches:
wherein the second-level drain electrodes (706 in second layer of electrodes in first active area) and the second-level source electrodes (704 in second layer of electrodes in first active area) associated with the first active area are arranged, with respect to the axis of symmetry, in a manner symmetrical, to the second-level drain electrodes (706 in second layer of electrodes in second active area) and to the second-level source electrodes (704 in second layer of electrodes in second active area) associated with the second active area (see Fig. 5 for layout of multiple cells (active layers). This layout applied to the embodiment of Fig. 8 includes the claimed relationship);
and the second-level drain electrodes being arranged alternating, along the axis of symmetry, with the second-level source electrodes (704 and 706 alternate in the direction of the axis of symmetry).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Mizan-623 in view of Mizan-141 as explained above.
With respect to claim 15, Mizan-623 teaches all limitations of claim 14 upon which claim 15 depends, Mizan-623 further teaches:
forming a first level of metallization; and from the first level of metallization forming: the first conductive bus (M1 which, includes gate bus 216);
forming a second level of metallization above first level of metallization; and from the second level of metallization forming: the second conductive bus (M2, which includes source bus 212);
Mizan-623 fails to teach:
first-level drain and source electrodes, extending transversely to the first conductive bus, configured to provide, respectively, drain electric potentials and source electric potentials of the power device to the first active area and to the second active area;
second-level source electrodes, extending from the second conductive bus in opposite directions with respect to the axis of symmetry and transversely to the second conductive bus, electrically connected to the first-level source electrodes; and second-level drain electrodes, extending transversely to the second conductive bus and electrically connected to the first-level drain electrodes.
Mizan-141 teaches in Fig. 8:
first-level drain and source electrodes (drain finger electrodes 706 and source finger electrodes 704), extending transversely to the first conductive bus (719), configured to provide, respectively, drain electric potentials and source electric potentials of the power device to the first active area and to the second active area;
Mizan further teaches:
“M1, M2 may each comprise more than one metal layer, for example a first metal layer defines the gate buses and source and drain finger electrodes and a second metal layer defines source and drain finger electrodes.” (Para 64)
second-level source electrodes (source finger electrodes in M2), extending from the second conductive bus (724) in opposite directions with respect to the axis of symmetry and transversely to the second conductive bus, electrically connected to the first-level source electrodes;
and second-level drain electrodes (drain finger electrodes in M2), extending transversely to the second conductive bus (724) and electrically connected to the first-level drain electrodes.
Mizan-623 discloses the claimed invention except for the limitations regarding what level of metallization the source and drain electrodes are formed on. Mizan-141 teaches that it is known to form source and drain metallization in the first layer and second layer with the relationship to the bus as claimed. It would be obvious to one of ordinary skill in the art to modify Mizan-623 by Mizan-141 to make source and drain fingers extending transverse to the gate bus in the first metallization layer for the purpose of optimizing current density within the electrodes (abstract). See MPEP 2144.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Mizan-623 (US 2019/0081623 A1) and Mizan-141 (US 2019/0081141 A1) as applied to claim 7 above and further in view of Lotfi (US 2014/0159130 A1).
With respect to claim 8, Mizan-623/Mizan-141 teaches all limitations of claim 7 upon which claim 8 depends. Mizan-623/Mizan-141 fails to teach:
comprising a third level of metallization, superimposed on the second level of metallization, provided with:
a drain metallization region, superimposed on the first active area;
a source metallization region, superimposed on the second active area;
third-level drain electrodes and third-level source electrodes, extending transversely to the axis of symmetry starting from the drain metallization region and from the source metallization region, respectively;
and the third-level drain electrodes being arranged alternating, along the axis of symmetry, with the third-level source electrodes.
Lotfi teaches in Figs. 12 and 14:
comprising a third level of metallization (source strips 1160, drain strips 1161, source contact 1170, and drain contact 1171), superimposed on the second level of metallization (1111 and 1121,), provided with:
a drain metallization region (drain contact 1171), superimposed on the first active area;
a source metallization region (source contact 1170), superimposed on the second active area;
third-level drain electrodes (1161) and third-level source electrodes (1160), extending transversely to the axis of symmetry (see annotated Fig. 14 below) starting from the drain metallization region and from the source metallization region, respectively;
and the third-level drain electrodes being arranged alternating, along the axis of symmetry, with the third-level source electrodes (see Fig. 12).
The Examiner takes the position that the source strips and drain strips 1111 and 1121 of Lotfi are analogous to the source and drain fingers of Mizan-141 which may be deposited in two layers. The Examiner therefore maps the elements 1160, 1161, 1170, and 1171 to the “third level of metallization” of the claimed invention despite the strips 1111 and 1121 being comprising one level of metallization in Lotfi as Mazin-623/Mazin-141 further modified by Lotfi would lead to the metallization of Lotfi being in the third level of metallization.
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Mazin-623/Mazin-141 discloses the claimed invention except for the third level of metallization including source and drain metallizations as claimed. Lotfi teaches that it is known to include a source and drain pad in different active areas on either side of a gate bus with metallizations extending from the pads toward and across the bus as shown in Figs. 12 and 14. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Mazin-623/Mazin-141, as taught by Lotfi in order to connect the sources and drains of the individual transistors to the control wiring. See MPEP 2144.
With respect to claim 9, Lotfi further teaches in Fig. 19:
comprising second-level conductive vias between the first level of metallization and the second level of metallization and third-level conductive vias between the second level of metallization and the third level of metallization (see Fig. 19, each level of metallization is connected to the lower level through a via, such as 1920, 1925, or 1930).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Mizan-623 in view of Mizan-141 and Lotfi as explained above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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