Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim of priority to Republic of Korea Patent Application No. 10-2023-0121471 filed on September 13, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 21, 2024, May 22, 2025, and August 21, 2025 are being considered by the examiner.
Drawings
The drawings are objected to because the drawings do not clearly show every feature of the inventions specified in the claims. In Figs. 4 and 7, it is not clear what the arrows associated with many of the element labels are pointing to. Claim 6 recites six first transistors, however only three first transistors T1 are labelled and it is not clear what elements two of the T1 labels are pointing to. Claim 7 recites three second transistors, however only two second transistors T2 are labeled. Claim 8 recites three driving transistors, however only two driving transistors DT are labeled. It is also not clear in Fig. 4 and 7 which elements are associated with which subpixel. Further, reference character SP (SP1, SP2, and SP3) is used to designate both main sub pixels and redundancy sub pixels. Claim 15 recites that the first active layer of the first transistor is below the power line and connected to the power line through a contact hole, however Fig. 5 and 8 only show the relationship between the driving transistor and the power line and does not show the first transistor.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 15 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 15 recites a relationship between the power line and first transistor that is not enabled. Although the claim language appears in para. [00149] of the written description, the written description requirement is not necessarily met when the claim language appears in ipsis verbis in the specification (MPEP 2163.03(V)). The relationship between the low potential power line VSS and the first transistor was not clearly described in the specification and it is therefore unclear how the first source electrode and first active layer are connected to the low potential power line. The relationship between these elements is also not clearly shown in the drawings.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 20, there is no antecedent basis for “the display device,” “the signal line,” “the driving transistor,” or “the power line.” The claim appears to be drafted to be dependent on claim 19, however no recitation of dependence appears in the claim. Claim 20 also recites “the driving transistor the power line” without a relationship between the elements. For the purpose of compact prosecution, the Examiner will treat claim 20 as though it reads “The display device of claim 19, wherein, in a cross-sectional view, the signal line is between the driving transistor and the power line and overlaps the driving transistor and the power line.”
Claim 20 is further rejected for indefiniteness because it is unclear whether the power line referenced in claim 20 is the same as the power line referenced in claim 19 which provides antecedent basis if claim 20 is meant to depend on claim 19 as the Examiner believes. The Examiner notes that only the power line VSS appears to meet the limitations of independent claim 19 and only power line VDD appears to meet the limitations of claim 20. The Examiner suggests amending to clarify whether the “power line” is meant to include both VSS and VDD or whether the power lines of claims 19 and 20 are the same power line.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 8-9 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (KR 20220091348 A1).
With respect to claim 1, Kim teaches:
A display device, comprising:
a substrate (substrate 111) including a plurality of pixel areas (plurality of pixels P) that are spaced apart from each other and a plurality of transmissive areas (transmission area TA) between the plurality of pixel areas,
wherein each of the plurality of pixel areas (P1 or P2, for example) includes a plurality of sub pixels (subpixels SP1, SP2, SP3, SP4);
and a plurality of signal lines (signal lines SL2) that extend in a first direction on the substrate (Y),
wherein the plurality of sub pixels include a plurality of pixel circuits para. 51 “Each of the first subpixel (SP1), second subpixel (SP2), third subpixel (SP3), and fourth subpixel (SP4) arranged as described above may be equipped with a circuit element including a capacitor, a thin-film transistor, etc., a plurality of signal lines supplying a signal to the circuit element, and a light-emitting element.
The thin-film transistor may include a switching transistor, a sensing transistor, and a driving transistor (TR1, TR2, TR3, TR4)“),
wherein the plurality of signal lines (SL2) overlap the plurality of pixel circuits without the plurality of signal lines overlapping the plurality of transmissive areas (see Fig. 4, TA is free of signal lines).
With respect to claim 3, Kim further teaches:
wherein the plurality of signal lines includes at least one of a plurality of data lines and a plurality of reference lines (para. 41 “Multiple second signal lines (SL2) can be extended in a second direction (Y-axis direction). Each of the plurality of second signal lines (SL2) may include at least one data line (DL1, DL2, DL3, DL4), a pixel power line (VDDL), a reference line (REFL), and a common power line (VSSL)”.)
With respect to claim 4, Kim further teaches:
wherein each of the plurality of sub pixels further includes (Fig. 13A: para. 141 “each subpixel (SP1, SP2, SP3, SP4) may include a first switching transistor (STR1), a second switching transistor (STR1), a driving transistor (DTR), a capacitor (Cst), and an organic light-emitting diode (OLED)”):
a first transistor (switching transistors STR1) between a data line from the plurality of data lines (Vdata) and the substrate, the first transistor (STR1) electrically connected to the data line (Vdata);
a driving transistor (driving transistor DTR) between the data line and the substrate, the driving transistor electrically connected to the first transistor (STR1, Fig. 13A shows the source of STR1 connected to the gate of DTR);
a second transistor (second switching transistor STR2) between the data line and the substrate, the second transistor electrically connected to the driving transistor (DTR) (Fig. 13 shows the source of DTR connected to the source of STR2);
a storage capacitor (capacitor Cst) between the data line (Vdata) and the substrate, the storage capacitor electrically connected to a gate electrode of the driving transistor (connected to gate note VG which is connected to DTR);
and a light emitting diode (OLED) over the data line, the light emitting diode electrically connected to the driving transistor (connected to the source of DTR).
With respect to claim 8, Kim further teaches:
wherein in one pixel area among the plurality of pixel areas,
the driving transistor (TR1) of the first sub pixel, the driving transistor (TR2) of the second sub pixel, and the driving transistor (TR3) of the third sub pixel are disposed in one line along the first direction (vertical direction).
With respect to claim 9, Kim further teaches:
wherein in one pixel area among the plurality of pixel areas,
the light emitting diode of the first sub pixel, the light emitting diode of the second sub pixel, and the light emitting diode of the third sub pixel are disposed in one line along the first direction (light emitting diodes are defined by anode electrode 120, light emitting layer 130, and cathode electrode 140. Fig. 8 shows the location of 120 within the cell, which is above the transistor TR and the lines DL1, DL2, DL3, and DL4. These elements in different subpixels are arranged along the first direction.)
With respect to claim 16, Kim further teaches:
wherein the reference lines (reference line REFL) are electrically connected to the second transistor (STR2, connected to reference voltage Vref),
and the reference lines (REFL) are disposed in the same level as that of the data lines (DL1-4)(see Fig. 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (KR 20220091348 A1) as applied to independent claim 1 above and further in view of Iwakawa (US 2023/0246005 A1).
With respect to claim 2, Kim further teaches:
a scan line (scan line SL1) that extends in a second direction (X) across the plurality of pixel areas on the substrate, the second direction (X) different from the first direction (Y),
wherein the plurality of sub pixels of each of the plurality of pixel areas include a first main sub pixel (SP1 of second pixel P2), a second main sub pixel (SP2), and a third main sub pixel (SP3) at a first side of the scan line (SL1)
wherein the first main sub pixel emits a first color of light (SP1 is a red sub-pixel), the second main sub pixel emits a second color of light (SP2 is a white sub-pixel), and the third main sub pixel emit a third color of light (SP3 Is a blue sub-pixel).
Kim fails to teach:
and a first redundancy sub pixel, a second redundancy sub pixel, and a third redundancy sub pixel at a second side of the scan line,
wherein the first main sub pixel and the first redundancy sub pixel emit a first color of light, the second main sub pixel and the second redundancy sub pixel emit a second color of light, and the third main sub pixel and the third redundancy sub pixel emit a third color of light.
Iwakawa teaches in para. 90 that the array includes a second redundant subpixel 52 next to the subpixel 51 in which there are two cells of each color 6R, 6B, 6G emitting the same light in both the subpixel and the redundant cell. Modifying Kim by Iwakawa such that the second pixel below the scan line is a redundant cell teaches:
and a first redundancy sub pixel (SP1 of P3 of Kim modified to be a redundant cell), a second redundancy sub pixel (SP2 of P3 of Kim modified to be a redundant cell), and a third redundancy sub pixel (SP3 of Kim modified to be a redundant cell) at a second side of the scan line (bottom side of SL1),
wherein the first main sub pixel and the first redundancy sub pixel emit a first color of light, the second main sub pixel and the second redundancy sub pixel emit a second color of light, and the third main sub pixel and the third redundancy sub pixel emit a third color of light (Iwakawa teaches that each subpixel and a corresponding redundant sub pixel emit a same color).
Kim discloses the claimed invention except for some of the subpixels being redundancy sub pixel. Iwakawa teaches that it is known for adjacent pixels in a display to include subpixels and redundancy subpixels that emit the same light as the main pixels. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim to include redundancy subpixels on one side of a scan line as taught by Iwakawa, Iwakawa states in para. 91 that such a modification would allow the pixel to continue working even if there is a defect in one of the subpixels. See MPEP 2144.
Claims 5, 7, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (KR 20220091348 A1).
With respect to claim 5, Kim does not label in Fig. 12 where the first transistors STR1 of the subpixels are located. However, Fig. 13a shows that the drain of STR1 is connected to the data line, the source is connected to the gate of the drive transistor, and the gate is connected to the Scan line. The scan line SCANL1 or SCANL2 runs along a second direction (X) different from the first direction (Y) and the drive lines associated with the first through fourth subpixels are also arranged along the second direction. Because the first transistors are connected to the Scan line, it would be obvious for at least part of the first transistors such as the gate electrodes to be arranged in a line along the X direction, meeting the limitation:
wherein in one pixel area among the plurality of pixel areas,
the first transistor (STR1) of the first sub pixel (SP1),
the first transistor (STR1) of the second sub pixel (SP2),
and the first transistor (STR1) of the third sub pixel (SP3) are disposed in one line along a second direction (X) that is different from the first direction (Y).
It would be obvious to modify Kim to meet the above limitation for the purpose of improving the efficiency of the circuit layout and because it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
With respect to claim 7, Kim does not label in claim 12 where the second transistors are in the plan view. However, Fig. 13 shows that the source or drain of STR2 is connected to the reference line and the other s/d is connected to the driving transistor. It would be obvious to arrange at least part of the second transistor of each sub pixel between the reference line and the driving transistor of the sub pixel, which meets the limitation:
wherein in one pixel area among the plurality of pixel areas,
the second transistor (STR2) of the first sub pixel (SP1),
the second transistor (STR2) of the second sub pixel (SP2),
and the second transistor (STR3) of the third sub pixel (SP3) are disposed in one line along the first direction (at least partially disposed along REFL).
It would be obvious to modify Kim to meet the above limitation for the purpose of improving the efficiency of the circuit layout and because it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
With respect to claim 17, Kim does not teach:
wherein the reference lines are integrally formed with a second drain electrode of the second transistor.
However, as explained in the rejection of claim 16 above, Kim teaches that the reference line (Vref) is connected to the drain of the second transistor (STR2). Drain electrodes and reference lines are both made from conductive materials and the elements are directly coupled as taught by the circuit diagram in Fig. 13A. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the two elements integrally, since it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. In re Larson, 144 USPQ 347, 349 (CCPA 1965). See MPEP 2144.04. The ordinary artisan would be motivated to make such a modification because forming the interconnected conductive parts as a single element may simplify the manufacturing process.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (KR 20220091348 A1) as applied to independent claim 5 above and further in view of Iwakawa (US 2023/0246005 A1) and Zhang (US 2025/0006122 A1).
With respect to claim 6, Kim teaches all limitations of claim 5 upon which claim 6 depends. Kim fails to teaches:
wherein in the one pixel area, a scan line includes a protruding part that protrudes from the scan line in the first direction and at least partially extends in the second direction, the first transistor of a first main sub pixel, the first transistor of a second main sub pixel, and the first transistor of a third main sub pixel at a first side of the scan line are on the protruding part of the scan line,
and the first transistor of a first redundancy sub pixel, the first transistor of a second redundancy sub pixel, and the first transistor of a third redundancy sub pixel at a second side of the scan line are on the scan line,
Iwakawa teaches that it is known for redundancy sub pixels emitting the same light to be disposed near main sub pixels.
It would be obvious to modify Kim by Iwakawa so that the sub pixels of pixel P2 of Kim are main subpixels and the sub pixels of pixel P3 of Kim are redundancy sub pixels. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim to include redundancy subpixels on one side of a scan line as taught by Iwakawa, Iwakawa states in para. 91 that such a modification would allow the pixel to continue working even if there is a defect in one of the subpixels. See MPEP 2144.
Zhang teaches in Fig. 6A that it is known for transistors to be controlled by the same line to include transistors one line to be controlled in a line along the second direction and for the transistors along another line of the second direction to be controlled by a protrusion that protrudes from the first line in the first direction and extends in the second direction. Applying this teaching to Kim/Iwakawa teaches:
wherein in the one pixel area (P2 of Kim), a scan line includes a protruding part (analogous to Gate2 of Fig. 6 of Zhang) that protrudes from the scan line (SL1 of Kim, analogous to Reset3 in the construction of Zhang) in the first direction and at least partially extends in the second direction (see Fig. 6A of Zhang), the first transistor of a first main sub pixel (STR1 of SP1), the first transistor (STR1 of SP2) of a second main sub pixel, and the first transistor (STR1 of SP3) of a third main sub pixel at a first side of the scan line (top side of SL1) on the protruding part of the scan line,
and the first transistor of a first redundancy sub pixel (STR1 of SP1 of P3), the first transistor of a second redundancy sub pixel (STR1 of SP2 of P3), and the first transistor of a third redundancy sub pixel (STR1 of SP3 of P3) at a second side of the scan line are on the scan line,
Claim 6 is rejected under the rational “Known Work in One Field of Endeavor May Prompt Variations of It for Use in Either the Same Field or a Different One Based on Design Incentives or Other Market Forces if the Variations Are Predictable to One of Ordinary Skill in the Art.” The Graham factual inquiries for this rationale are:
(1) a finding that the scope and content of the prior art, whether in the same field of endeavor as that of the applicant’s invention or a different field of endeavor, included a similar or analogous device (method, or product);
(2) a finding that there were design incentives or market forces which would have prompted adaptation of the known device (method, or product);
(3) a finding that the differences between the claimed invention and the prior art were encompassed in known variations or in a principle known in the prior art;
(4) a finding that one of ordinary skill in the art, in view of the identified design incentives or other market forces, could have implemented the claimed variation of the prior art, and the claimed variation would have been predictable to one of ordinary skill in the art; and
(5) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
The device of Kim/Iwakawa teaches a device in which two transistors of the main subpixel and redundancy subpixel are controlled by a same scan line to emit a same light. Zhang teaches an analogous construction in which two transistors of different subpixels are controlled along a same line in which one of the transistors is connected to a part of the line that protrudes in the first direction and then turns in the second direction. There would be design incentives to adapt the adaptation of the wiring structure of Zhang to the device of Kim Iwakawa to optimize the layout of wires to improve integration of the device. The differences in the layout of the wiring of Kim and the claimed invention is taught by the device of Zhang. One of ordinary skill in the art with an incentive to optimize the layout of the wires of the device of Kim/Iwakawa could have implemented the change to the shape of the wiring to include a protrusion in the scan line to connect to the transistors of the second subpixel with predictable results of connecting the scan line to the pixels of both the main transistor and redundancy transistor such that both the main and redundancy subpixels emit a same light at the same time as taught by Iwakawa.
Claim 10-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (KR 20220091348 A1) in view of Jeong (US 2022/0173184 A1).
With respect to claim 10, Kim teaches all limitations of claim 4 upon which claim 10 depends. Kim fails to teach:
wherein the plurality of signal lines are over the driving transistor and the storage capacitor and overlap the driving transistor and the storage capacitor.
Jeong teaches:
wherein the plurality of signal lines (signal lines including data line DL, scan lines SL1, SL2, SL3, SL4) are over the driving transistor (driving transistor T1) and the storage capacitor (storage capacitor Cst, at least part DL is disposed over the storage line and capacitor) and overlap the driving transistor and the storage capacitor (overlaps gate G1 of the transistor and capacitor CE1).
With respect to claim 11, Kim teaches all limitations of claim 4 upon which claim 11 depends. Kim further teaches:
a buffer layer (buffer layer BF) between the substrate (substrate 111) and the driving transistor (TR);
a gate insulating layer (GI) on the buffer layer (BF),
the gate insulating layer between a driving gate electrode (GE) and a driving active layer (ACT) of the driving transistor;
a first interlayer insulating layer (ILD) that covers the driving transistor;
Kim fails to teach:
and one or more insulating layers that cover the storage capacitor on the first interlayer insulating layer,
wherein the plurality of signal lines are on the one or more insulating layers and a thickness of the one or more insulating layers is larger than a thickness of the buffer layer, a thickness of the gate insulating layer, and a thickness of the first interlayer insulating layer.
Jeong teaches in Fig. 4:
and one or more insulating layers (114, 115, 116) that cover the storage capacitor (CE2) on the first interlayer insulating layer (113),
wherein the plurality of signal lines (DL) are on the one or more insulating layers and a thickness of the one or more insulating layers is larger than a thickness of the buffer layer (111), a thickness of the gate insulating layer (112), and a thickness of the first interlayer insulating layer (113).
Kim discloses the claimed invention except for the relationship and arrangement of the different layers of the pixel circuit. Jeong teaches that it is known to stack the layers of insulating layers, capacitors, and signal lines as claimed. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the layers of the pixel circuit to increase the number of layers such that the lines are over the capacitor and transistor with insulating layers between for the purpose of increasing the integration and reducing the power consumption of the pixel circuit (para. 6 of Jeong) and/or since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
With respect to claim 12, Kim teaches all limitations of claim 4 upon which claim 12 depends. Kim fails to teach:
a power line between the storage capacitor and the plurality of signal lines, the power line overlapping the plurality of signal lines.
Jeong teaches in Fig. 4:
a power line (PL1) between the storage capacitor (Cst) and the plurality of signal lines (at least DL of the plurality of signal lines), the power line overlapping the plurality of signal lines (PL1 overlaps DL in the vertical direction).
Kim discloses the claimed invention except for the relationship and arrangement of the different layers of the pixel circuit. Jeong teaches that it is known to stack the layers of lines as claimed. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the layers of the pixel circuit to increase the number of layers such that the lines are over the capacitor and transistor with insulating layers between for the purpose of increasing the integration and reducing the power consumption of the pixel circuit (para. 6 of Jeong) and/or since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
With respect to claim 13, Jeong teaches that there are two power supplies, PL1 and PL2, and that PL1 supplies power supply voltage ELVDD and that PL2 supplies ELVSS. Although Jeong does not explicitly state which is a higher potential power, the ordinary artisan would understand that “VDD” typically refers to the high power supply. Therefore, Jeong teaches:
wherein the power line includes a low potential power line or a high potential power line (PL1 attached to ELVDD).
In the event that ELVDD being the high power supply is not implicit, which the Examiner does not concede, it would be obvious for PL1 to either carry the high power supply or the low power supply because whatever the potential ELVDD is may be considered either high or low because the limits of “high” and “low” potential are not clearly defined and the Examiner considers the recitation of “high power potential” or “low power potential” to include any potential.
With respect to claim 14, Jeong further teaches:
wherein the power line (PL1) overlaps the driving transistor (G1 of T1) and the storage capacitor (CE1 of Cst, right end of PL1 overlaps with left end of CE1/G1 in the vertical direction).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Kim in view of Jeong as explained above.
With respect to claim 15, Jeong further teaches:
wherein a driving active layer (first semiconductor layer AS1) of the driving transistor (T1) and a first active layer (second semiconductor layer AS2) of the first transistor (second transistor T2 which is a switching transistor) are below the power line (PL1), a driving drain electrode (D1) of the driving transistor (T1) and a first source electrode (S2) of the first transistor (T2) are on the power line (D1 and S2 can be considered “on” the power line because they are connected to the power line at least indirectly through Cst and T5),
and the power line includes a plurality of openings that overlap a contact hole through which the driving active layer and the driving drain electrode are connected and a contact hole (contact hole 11) through which the first active layer and the first source electrode are connected.
Kim/Jeong discloses the claimed invention except for the relationship and arrangement of the different layers of the pixel circuit. Jeong further teaches that it is known to arrange and connect the layers of the pixel circuit as claimed. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the layers of the pixel circuit to increase the number of layers such that the lines are over the capacitor and transistor with insulating layers between for the purpose of increasing the integration and reducing the power consumption of the pixel circuit (para. 6 of Jeong) and/or since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
With respect to claim 19, Kim teaches:
A display device comprising:
a substrate including a pixel area (pixels P) and a light transmitting area (transmissive area TA) that is more transparent than the pixel area;
a driving transistor (driving transistor TR1) in the pixel area;
a light emitting element (light emitting devices including an anode electrode 120, light emitting layer 130, and cathode electrode 140) in the pixel area,
the light emitting element electrically connected to the driving transistor (see Fig. 13a, driving transistor DTR is directly connected to OLED).
Kim fails to teach:
a power line over the driving transistor in the pixel area; a signal line over the power line in the pixel area;
Jeong teaches:
a power line (power supply voltage line PL1) over the driving transistor (first transistor T1) in the pixel area; a signal line (data line DL) over the power line (PL1) in the pixel area;
Kim teaches the claimed invention except for the arrangement of the power and signal lines with respect to each other and the driving transistor. Jeong teaches that it is known to arrange the power line above the driving transistor and the signal line above the power line. It would be obvious to the ordinary artisan to modify Kim with Jeong to arrange the lines over the driving transistor for the purpose of reducing the footprint of the pixel circuit by vertically stacking the layers and since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
With respect to claim 20, Kim further teaches:
the signal line (data lines DL1-DL4) is between the driving transistor (TR1-TR4) and the power line (VSSL) and overlaps the driving transistor the power line (see Fig. 7, the elements overlap in the X direction).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (KR 20220091348 A1) in view of Furuie (US 2015/0214280 A1).
With respect to claim 18, Kim teaches all limitations of claim 1 upon which claim 18 depends. Kim fails to teach:
wherein the plurality of sub pixels comprise:
a first sub pixel having a rectangular shape in a plan view of the display device;
a second sub pixel that encloses two adjacent sides among four sides of the first sub pixel in the plan view;
and a third sub pixel that encloses an outside part of the second sub pixel in the plan view, and wherein the first sub pixel, the second sub pixel,
and the third sub pixel collectively form a rectangular shape.
Furuie teaches in Fig. 4A:
wherein the plurality of sub pixels (W, G, R, and B) comprise:
a first sub pixel (W) having a rectangular shape in a plan view of the display device;
a second sub pixel (G) that encloses two adjacent sides among four sides of the first sub pixel in the plan view;
and a third sub pixel (R) that encloses an outside part of the second sub pixel in the plan view,
and wherein the first sub pixel, the second sub pixel, and the third sub pixel collectively form a rectangular shape (see Fig. 5A).
Kim discloses the claimed invention except for the arrangement of the subpixels. Furuie teaches that it is known to arrange sub pixels with the layout as claimed. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim as taught by Furuie, since Furuie states in para. [0044] that such a modification would prevent reduction of image quality due to color mixing. See MPEP 2144.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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