Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on an application filed in Japan on May 25, 2023, and receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. It should be noted that in order to effectively benefit from the foreign priority date, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--JFET Including An Ellipse-Shaped Field Plate With Spaced Apart Curved Line Portions With Uniform Resistance--
Claim Objections
Claim 2 is objected to because of the following informalities:
Regarding Claim 2, the preamble lacks a transitional phrase (e.g. ‘wherein’) to define the relation of the additional limitations of the dependent claim to the independent claim. Given the nature of the limitations and the nature of subsequent claims, it’s the Examiner’s understanding that the intent was for the preamble to include the term “wherein” but was simply forgotten as a typographical error.
For the purpose of this Office Action, the Examiner will read the preamble of Claim 2 as –The semiconductor device according to claim 1, wherein--
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, the limitation “virtual concentric ellipse” is unclear. In particular, the term “concentric” is an adjective (‘having a common center’ – Merriam-Webster Definition 1) describing compared subjects. In this case a singular virtual ellipse is given, but it itself cannot be concentric.
For the purpose of this Office Action, the Examiner will read the limitation “virtual concentric ellipse” of Claim 2 and 3 as –initial virtual ellipse--
Regarding Claims 3-5, the claims are rejected based on their dependency on Claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over Fujie et al. (U.S. 2017/0338354), hereinafter Fujie, in view of Hayashi (U.S. 2020/0411508), hereinafter Hayashi. For clarity, an annotated version of Hayashi Fig. 4, hereinafter Fig. 4A, is provided below.
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Regarding Claim 1, Fujie teaches a semiconductor device ((1) with JFET; Figs. 1A-5, Paragraph [0031]) comprising:
-a semiconductor substrate having a first conductivity type (‘p-type’ (2); Fig. 1A, Paragraph [0032]);
-a semiconductor layer located above the semiconductor substrate (2), the semiconductor layer having a second conductivity type (‘n-type’ (3); Fig. 1A, Paragraph [0032]);
-a drain region located in the semiconductor layer (3), the drain region having the second conductivity type (‘n-type’ (4); Fig. 1A and 1B, Paragraph [0033]);
-a source/gate region ((9); Fig. 1A, Paragraph [0036]) including a source region having the second conductivity type (‘n-type’ (7); Fig. 5, Paragraph [0037]) and a gate region electrically connected to the source region, the gate region having the first conductivity type (‘p-type’ (8); Fig. 4, Paragraph [0037]), the source/gate region (9) being spaced from the drain region (3) and located around the drain region (Fig. 1A and 2, Paragraph [0036]);
-an insulating layer ((12); Fig. 1A, Paragraph [0047]) located above the semiconductor layer (3) and between the drain region (4) and the source/gate region (9); and
-a field plate ((20); Figs. 1A and 2, Paragraph [0050]) located above the insulating layer (12), the field plate forming a current path (e.g. Paragraph [0053]), wherein the field plate includes an innermost periphery ((20a); Figs. 1a and 2, Paragraph [0051]) electrically connected to the drain region (4), an outermost periphery ((20b); Fig. 1a and 2, Paragraph [0051]) electrically connected to a ground (‘ground’)
Fujie does not explicitly teach:
-a first straight line portion and a second straight line portion located between the innermost periphery and the outermost periphery and adjacent to each other in a first direction in a plan view, and a first connection portion connecting the first straight line portion and the second straight line portion, wherein each of the innermost periphery, the outermost periphery, the first straight line portion, the second straight line portion and the first connection portion is a part of the current path, wherein each of the first straight line portion and the second straight line portion extends in a second direction intersecting with the first direction in a plan view, and wherein the first connection portion extends in the first direction.
Hayashi teaches a semiconductor device ((10) with JFET; Figs. 4-6, Paragraph [0054]) comprising:
-a field plate (‘FP’ e.g. consisting of (240) and (250); Figs. 4A, 5, and 6, Paragraph [0044]) located above an insulating layer ((230); Figs. 5 and 6, Paragraph [0054])
-the field plate forming a current path (e.g. Paragraph [0050]), wherein the field plate includes an innermost periphery ((IP); Figs. 4A) electrically connected to the drain region ((310); Fig. 4A-6, Paragraph [0068])
-an outermost periphery ((OP); Fig. 4A) electrically connected to a ground (via (320); Paragraph [0071])
-a first straight line portion ((1S); Fig. 4A)) and a second straight line portion ((2S); Fig. 4A) located between the innermost periphery (IP) and the outermost periphery (OP) and adjacent to each other in a first direction in a plan view (X-direction, Fig. 4A), and a first connection portion ((1C); Fig. 4A) connecting the first straight line portion (1S) and the second straight line portion (2S), wherein
-each of the innermost periphery (IP), the outermost periphery (OP), the first straight line portion (1S), the second straight line portion (2S) and the first connection portion (1C) is a part of the current path (of the total field plate ‘FP’), wherein
-each of the first straight line portion (1S) and the second straight line portion (2S) extends in a second direction (Y-direction, Fig. 4A) intersecting with the first direction (X-direction) in a plan view, and wherein the first connection portion (1C) extends in the first direction (X-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hayashi into the device of Fujie such that the field plate includes a first straight line portion and a second straight line portion located between the innermost periphery and the outermost periphery and adjacent to each other in a first direction in a plan view, and a first connection portion connecting the first straight line portion and the second straight line portion, wherein each of the innermost periphery, the outermost periphery, the first straight line portion, the second straight line portion and the first connection portion is a part of the current path, wherein each of the first straight line portion and the second straight line portion extends in a second direction intersecting with the first direction in a plan view, and wherein the first connection portion extends in the first direction. This would be due to the fact that doing so would incorporate a viable field plate structure resulting in further stabilized current between the drain and source electrodes while reducing power consumption (Hayashi, Paragraphs [0068] and [0076]).
Regarding Claim 2, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 1, wherein:
-each of the innermost periphery (Hayashi, (IP)), the outermost periphery (Hayashi, (OP)), the first straight line portion (Hayashi (1S)) and the second straight line portion (Hayashi, (2S)) is disposed on an initial virtual ellipse centered on the drain region (Fujie, (4), compare to Hayashi, (310)).
Examiner notes that without rigidly defining the nature of the virtual ellipse (e.g. is an outline (not counting the interior space), etc.) and each element’s relation to it (e.g. cannot extend beyond, must be formed on the boundary, etc.), an arbitrary ellipse may be formed such that each element is disposed on it.
Regarding Claim 6, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 1, wherein:
-the first connection portion (Hayashi, (1C)) is connected to one end (top end, positive Y-direction) of the first straight line portion (Hayashi, (1S)) in the second direction.
Regarding Claim 7, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 6, wherein:
-the innermost periphery (Hayashi, (IP)) includes a third straight line portion (Hayashi, (3S); Fig. 4A) adjacent to the first straight line portion (Hayashi, (1S)) in the first direction (X-direction), wherein the field plate further includes a second connection portion (Hayashi, (2C)) connecting the first straight line portion (Hayashi, (1S)) and the third straight line portion (Hayashi, (3S)), and wherein the second connection portion (Hayashi, (2C)) is connected to the other end (bottom end, negative Y-direction) of the first straight line portion (Hayashi, (1S)) in the second direction.
Regarding Claim 8, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 1, wherein:
-at least one of the innermost periphery and the outermost periphery has an oval shape in a plan view (in this case, the innermost periphery of Hayashi (IP), compare also Fujie (20a))
Regarding Claim 9, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 1, wherein:
-at least one of the innermost periphery and the outermost periphery (in this case, the innermost periphery of Hayashi (IP)) has a straight line portion (Hayashi, (3S); Fig. 4A) and a curved line portion (Hayashi, (CP); Fig. 4A) spaced apart from each other (in the X-direaction), and wherein the straight line portion (Hayashi, (3S)) and the curved line portion (Hayashi, (CP)) are electrically connected via a conductive member (Hayashi, (260); Figs. 4A-6, Paragraph [0068]) located above the field plate (Hayashi, (FP)).
Regarding Claim 10, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 1, wherein:
-the field plate includes polysilicon (Fujie, Paragraph [0052], also Hayashi, Paragraph [0067]).
Regarding Claim 11, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 1, wherein:
the semiconductor layer (Fujie, (3)) further includes:
-a gate well region in contact with the gate region (Fujie, (8)), the gate well region having the first conductivity type (Fujie, ‘p-type’ (11); Fig. 4, Paragraph [0042]); and
-a source well region in contact with the source region (Fujie, (7)), the source well region having the second conductivity type (Fujie, ‘n-type’ (10); Fig. 5, Paragraph [0039]), and wherein
-the source well region includes a projected portion (Fujie, (10a); Fig. 4, Paragraphs [0039] and [0040]) projecting toward the drain region (Fujie, (4)) more than the gate well region (Fujie, (11)).
Regarding Claim 12, Fujie as modified by Hayashi ((10) with JFET; Figs. 4-6, Paragraph [0054]) of Claim 11, wherein:
-in a plan view, the outermost periphery (Hayashi, (OP) as incorporated into Fujie) is located closer to the drain region (Fujie, (4)) than the projected portion (Fujie, (10a)) – (Necessarily by incorporation, being the outer periphery).
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and including corrections to address 112b rejections and minor informality objections.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in defining the structure, a semiconductor device comprising:
-the first curved line portion and the second curved line portion being spaced apart from the innermost periphery, the outermost periphery, the first straight line portion and the second straight line portion
-the first straight line portion and the first curved line portion are located on a first virtual ellipse included in the initial virtual ellipse, and wherein
the second straight line portion and the second curved line portion are located on a second virtual ellipse included in the initial virtual ellipse.
Regarding Claims 4-5, the claims are allowable based on their dependence on Claim 3.
Closest prior art references found during examination are listed below:
U.S. Pub. 2017/0338354 U.S. Pub. 2019/0165167 U.S. Pub. 2020/0411508
These references disclose similar semiconductor devices (JFET) which incorporate the various patterns of field plates. However, in none of the cases is there a teaching to establish a field plate structure with the limitations noted above.
In regards to the limitation, the Examiner notes that the structural features established by these limitations are well described in the instant application in Paragraphs [0046]-[0049] and Figs. 4 and 5, and the inclusion of such features is not considered arbitrary or a simple choice of element shape.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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