DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are:
It is clear from the disclosure that Applicant considers the embodiments of Figs 6 and 7 to be the invention. The trench formed in claim 1 requires an inverted trapezoidal trench (from claim 2) and angle between the sidewall and the bottom surface of the trench to be greater than or equal to 90 degrees. This would be met with the staircase-shaped trench. Claims 3-5 form a staircase-shaped trench (Fig 2 of instant application) when complete, there being no additional steps to smooth trench for forming a smooth inverted trapezoidal trench. For purposes of examination, Examiner will interpret the additional steps in the specification to have been carried out to form the trench of Fig 4.
Claims 4-5 are also rejected as they are dependent on claim 3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et. al. (US 20230326972 A1), hereinafter Chen.
Regarding claim 1, Chen teaches a method of manufacturing (Figs 3A-3L, [0049]) a semiconductor device (Fig 3A not labeled semiconductor power transistor, [0040]), comprising: forming ([0050]) a trench (Fig 3A V-groove 304, [0050]) in a substrate (Fig 3A substrate 300, [0041]), the trench (Fig 3A V-groove 304, [0050]) extending downwards from a top surface (Fig 3A top surface 303A, [0050]) of the substrate (Fig 3A substrate 300, [0050]), wherein the trench (Fig 3A V-groove 304, [0050]) has a sidewall (Fig 3A sidewall 304a, [0050]) and a bottom surface (Fig 3A bottom 304b, [0050]), and an angle (Fig 3A tilt angle θ1, [0050]) between the sidewall (Fig 3A sidewall 304a, [0050]) and the bottom surface (Fig 3A bottom 304b, [0050]) is greater than or equal to 90 degrees (Fig 3A tilt angle θ1 is less than 90 degrees so the complementary angle would be greater than 90 degrees, [0050]); forming ([0055]) a well region (Fig 3F well region 310a/b, [0055]) at the top surface (Fig 3F top surface 302A, [0050]) of the substrate (Fig 3F substrate 300, [0050]), the sidewall (Fig 3F sidewall 304a, [0050]) and the bottom surface (Fig 3F bottom 304b, [0050]) of the trench (Fig 3F V-groove 304, [0050]); forming ([0056]) a source region (Fig 3G source region 314, [0056]) at the bottom surface (Fig 3G bottom 304b, [0050]) of the trench (Fig 3G V-groove 304, [0050]); forming ([0058]) a body contact region (Fig 3I well pick-up region 318a, [0058]) at the bottom surface (Fig 3I bottom 304b, [0050]) of the trench (Fig 3I V-groove 304, [0050]), and the body contact region (Fig 3I well pick-up region 318a, [0058]) being adjacent (Fig 3I to the source region (Fig 3I source region 314, [0056]); forming ([0060]) a gate structure (Fig 3J gate layer 322, [0059]) along the top surface (Fig 3J top surface 302A, [0050]) of the substrate (Fig 3J substrate 300, [0050]), the sidewall (Fig 3J sidewall 304a, [0050]) and the bottom surface (Fig 3J bottom 304b, [0050]) of the trench (Fig 3J V-groove 304, [0050]); and forming ([0061]) a source contact (Fig 3L source electrodes 324a, [0061]) in the trench (Fig 3L V-groove 304, [0050]) to penetrate the gate structure (Fig 3L gate layer 322, [0059]) and electrically connect ([0061]) to the source region (Fig 3L source region 314, [0056]) and the body contact region (Fig 3L well pick-up region 318a, [0058]).
Regarding claim 2, Chen teaches the trench (Fig 3A V-groove 304, [0050]) is an inverted trapezoidal (Fig 3A) trench (Fig 3A V-groove 304, [0050]).
Regarding claim 6, Chen teaches the angle between the sidewall (Fig 3A sidewall 304a, [0050]) and the bottom surface (Fig 3A bottom 304b, [0050]) is determined based on a direction of lattice arrangement (the face of the V-grooves follows the underlying orientation plane of the substrate, [0050]) of the substrate (Fig 3A substrate 300, [0050]).
Regarding claim 7, Chen teaches a semiconductor device (Fig 2A not labeled semiconductor power transistor, [0040]), comprising: a substrate (Fig 2A substrate 100, [0041]) having a trench (Fig 2A V-groove 104, [0041]) extending downwards from a top surface (Fig 2A top surface 102a, [0041]) of the substrate (Fig 2A substrate 100, [0041]), wherein the trench (Fig 2A V-groove 104, [0041]) has a sidewall (Fig 2A sidewall 104a, [0042]) and a bottom surface (Fig 2A bottom 104b, [0043]) (Fig 2A bottom 104b, [0043]), and an angle (Fig 2A tilt angle θ1, [0043]) between the sidewall (Fig 2A sidewall 104a, [0042]) and the bottom surface (Fig 2A bottom 104b, [0043]) (Fig 2A bottom 104b, [0043]) is greater than or equal to 90 degrees (Fig 2A tilt angle θ1 is less than 90 degrees so the complementary angle would be greater than 90 degrees, [0043]); a gate structure (Fig 2A gate layer 110, [0041]) over the substrate (Fig 2A substrate 100, [0041]) and along (Fig 2A) the top surface (Fig 2A top surface 102a, [0041]) of the substrate (Fig 2A substrate 100, [0041]), the sidewall (Fig 2A sidewall 104a, [0042]) and the bottom surface (Fig 2A bottom 104b, [0043]) (Fig 2A bottom 104b, [0043]) of the trench (Fig 2A V-groove 104, [0041]); a source contact (Fig 2A source electrode 116a, [0041]) in the trench (Fig 2A V-groove 104, [0041]) of the substrate (Fig 2A substrate 100, [0041]) and penetrating (Fig 2A) the gate structure (Fig 2A gate layer 110, [0041]) to electrically connect to a source region (Fig 2A source region 108, [0041]) of the substrate (Fig 2A substrate 100, [0041]); and a drain electrode (Fig 2A drain electrode 120, [0045]) below the substrate (Fig 2A substrate 100, [0041]).
Regarding claim 8, Chen teaches the trench (Fig 2A V-groove 104, [0041]) is an inverted trapezoidal (Fig 2A) trench (Fig 2A V-groove 104, [0041]).
Regarding claim 9, Chen teaches a well region (Fig 2A well region 106a/b, [0041]) along the top surface (Fig 2A top surface 102a, [0041]) of the substrate (Fig 2A substrate 100, [0041]), the sidewall (Fig 2A sidewall 104a, [0042]) and the bottom surface (Fig 2A bottom 104b, [0043]) of the trench (Fig 2A V-groove 104, [0041]); and a body contact region (Fig 2A well pick-up region 114a, [0041]) at the bottom surface (Fig 2A bottom 104b, [0043]) (Fig 2A bottom 104b, [0043]) of the trench (Fig 2A V-groove 104, [0041]), and the body contact region (Fig 2A well pick-up region 114a, [0041]) being adjacent (Fig 2A) to the source region (Fig 2A source region 108, [0041]).
Regarding claim 10, Chen teaches an extending direction of the sidewall (Fig 2A sidewall 104a, [0042]) of the trench (Fig 2A V-groove 104, [0041]) is same as a direction of lattice arrangement (the face of the V-grooves follows the underlying orientation plane of the substrate, [0050]) of the substrate (Fig 2A substrate 100, [0041]).
Regarding claim 11, Chen teaches an extending direction of the gate structure over the sidewall (Fig 2A sidewall 104a, [0042]) of trench (Fig 2A V-groove 104, [0041]) is same as a direction of lattice arrangement (the gate structure is placed on the V-groove which follows the underlying orientation plane of the substrate, [0061]) of the substrate (Fig 2A substrate 100, [0041]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20230326972 A1), hereinafter Chen, in view of Zhang et. al (US 20230197448 A1), hereinafter Zhang, in further view of Sundararajan et. al. (US 20160203999 A1), hereinafter Sundar, with supporting evidence from Khazi et. al. (“3D free forms in c-Si via grayscale lithography and RIE,” Microelectronic Engineering 193, 34-40, 2018).
Regarding claim 3, Chen fails to teach wherein forming the trench in the substrate comprises: forming a plurality of staircase-shaped dielectric layer stacks over the substrate; and etching the substrate to form the trench by using the staircase-shaped dielectric layer stacks as masks.
However, Zhang teaches using a dielectric as a hardmask to provide high etch selectivity ([0034] and [0042]). Further, Zhang teaches forming a multi-level pattern in the dielectric and transferring the pattern onto the underlying substrate (Fig 2, [0033]). The muti-level pattern of Zhang is formed by patterning a photoresist and etching the dielectric ([0033]). Khazi shows a mask pattern to form a staircase shape in a substrate after etching (Fig 1). Sundar teaches an etch mask may comprise any number of layers and dielectrics ([0023]). Further, Sundar teaches in a multi-layered mask embodiment, mask features may be the result of both lithographic printing and dry etch processes ([0024]). In addition, Sundar teaches hardmask features are then transferred onto the substrate ([0025]). One having ordinary skill in the art before the effective filing date of the claimed invention would have combined, using routine experimentation, the single layer hardmask of Zhang with the multilayer mask of Sundar to achieve the staircase-shaped dielectric layer stacks of the claimed invention. One having ordinary skill in the art before the effective filing date of the claimed invention would have combined these teachings into Chen to provide the dielectric etch selectivity of Zhang ([0034] and [0042]). MPEP 2143(I)(G)
Regarding claim 4, Chen as modified in claim 3 teaches patterning (Sundar teaches in a multi-layered mask embodiment, mask features are a result of both lithographic printing and dry etching, [0024]) the dielectric layer stack by a photomask multiple times to form the staircase-shaped dielectric layer stacks.
Chen as modified in claim 3 fails to teach the dielectric layer stack comprising a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked, wherein the first dielectric layers are made of a first material, and the second dielectric layers are made of a second material different from the first material.
Regarding the dielectric layer stack comprising a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked, wherein the first dielectric layers are made of a first material, and the second dielectric layers are made of a second material different from the first material. This arrangement would have been obvious to try. Sundar teaches the multi-layer mask may have inorganic dielectrics such as silicon dioxide or silicon nitride ([0023]). Zhang, from above, teaches there is high etch selectivity for both silicon dioxide and silicon nitride ([0034] and [0042]). In pursing this arrangement in the substrate of Chen, two materially different dielectric layers can be alternately stacked. One having ordinary skill in the art would recognize that the desired etch selectivity would be achieved equally, regardless of which of these dielectric materials is chosen. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 5, Chen as modified in claim 3 fails to teach during etching the substrate by using the staircase-shaped dielectric layer stacks as the masks, the staircase-shaped dielectric layer stacks and the substrate are etched at a same etching rate.
However, Zheng teaches a deep silicon etching recipe was used with a high Si:SiO2 etch selectivity ([0040]). Further, Zhang teaches using different dielectric materials requires changing the process flow to quantify etch rates and selectivities specific to the tools and process conditions ([0042]). Further, Sundar teaches the etch process is a function of the composition of the material to be removed and other typical constraints. The selectivity of the dielectric to substrate is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the selectivity of the dielectric to substrate as Zhang and Sundar has identified the selectivity of the dielectric to substrate as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the staircase-shaped dielectric layer stacks and the substrate being etched at a same etching rate, in order to achieve the desired balance between the etch rate of the dielectric layer and the etch rate of the substrate, as taught by Zhang and Sundar. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed selectivity is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed selectivity).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sreenivasan et. al. (US 20160308020 A1) teaches a method to form a multi-tier pattern on an underlying substrate using a resist and hardmask as an etch mask.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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