DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on May 22, 2024 and March 26, 2025 were considered by the Examiner.
Election/Restrictions
Applicant's election without traverse of Species A and claims 1-4, 6-12 in the reply filed on July 14, 2026 is acknowledged. As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 10-11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 includes “the second drain/source contact layer” which lacks an antecedent basis. For the purposes of examination, this will be interpreted as “a second drain/source contact layer.”
Claims 10, 11 each include “a top side of the pickup N-well region is exposed to a surface of the semiconductor substrate” and this is indefinite because in each of these claims the pickup N-well region is part of the N-type region, which is part of the semiconductor substrate in claim 9. Accordingly, the pickup N-well region is part of the semiconductor substrate and it is unclear what the meaning of exposing it to a surface of the semiconductor substrate means. For the purposes of examination, this limitation will be interpreted to mean “a top side of the pickup N-well region is exposed from a surface of another part of the semiconductor substrate” since in FIG. 1L of the instant application, the top side of the pickup N-well region 104 is exposed from another part 101 or 103 of the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20170076757A1 (“Wu”) in view of US20210249421A1 (“Ou”), further in view of US20190287967A1 (“Liaw”), further in view of US20230049378A1 (“Chen”).
RE: Claim 1, Wu discloses An antifuse-type memory (memory array in FIG. 7, [0019]) comprising a first memory cell (2001,1, [0044]), the first memory cell being constructed on a substrate (substrate in FIG. 7), the first memory cell comprising:
a first select transistor (250, [0049]), wherein a first drain/source terminal (source or drain 258, [0052]) of the first select transistor is connected with a first bit line (BL1, [0050]), and a gate terminal (gate terminal 250G, [0049]) of the first select transistor is connected with a first word line (250 of cell 2001,1 has gate terminal coupled to word line WL1, [0026]; accordingly, gate terminal 250G is coupled to word line WL1);
a first following transistor (240, [0048]), wherein a first drain/source terminal (source or drain 248, [0052]) of the first following transistor is connected with a second drain/source terminal (source or drain 252, [0052]) of the first select transistor, and a gate terminal (gate terminal 240G, [0048]) of the first following transistor is connected with a first following control line (240 of cell 2001,1 has gate terminal coupled to following control line FL, [0026]; Accordingly, gate terminal 240G of 240 is coupled to the following control line FL); and
a first antifuse transistor (230, [0052]) comprising:
a first gate structure (gate terminal 230G, [0047]) comprising a first gate layer (230G), and the first gate layer is connected with a first antifuse control line (230 has gate terminal coupled to antifuse control line AF1, [0026]; accordingly, gate terminal 230G is coupled to antifuse control line AF1);
a first terminal (source or drain 238, [0052]), connected with a second drain/source terminal (source or drain 242, [0052]) of the first following transistor; and
a second drain/source terminal (234, [0047]) electrically connected with a second terminal (source or drain 232, [0052]).
Wu does not explicitly disclose:
the substrate is a semiconductor substrate;
the first antifuse transistor comprises:
a first fin;
the first gate structure of the first antifuse transistor comprises:
a first gate dielectric layer;
wherein the first gate dielectric layer covers a top surface and two lateral surfaces of a central region of the first fin, the first gate dielectric layer is covered by the first gate layer;
the first terminal is a terminal of the first fin;
a first drain/source contact layer electrically connected with the first terminal of the first fin, wherein the first drain/source contact layer is connected with the second drain/source terminal of the first following transistor;
the second terminal is a second terminal of the first fin;
wherein the first bit line receives a ground voltage, the first word line receives an on voltage, the first following control line receives a conducting voltage and the first antifuse control line receives a program voltage when a program action is performed, the first gate dielectric layer of the first antifuse transistor is ruptured, so that the first memory cell is programmed into a low-resistance storage state.
However, in Wu, the transistors 230, 240, 250 are connected in series.
Wu teaches the first select transistor 210, the first following gate transistor 520, the second select transistor 250, and the second following gate transistor 540 are formed by N-type metal-oxide-semiconductor field effect transistors, [0064].
In the same field of endeavor, Ou discloses:
Ante-fuse one-time programmable (OTP) devices according to some embodiments have an anti-fuse element connected to a transistor. Anti-fuses are incorporated in the design of the integrated circuits, [0022].
Ou further discloses embodiments are discussed below in the context of forming finFET transistors having a single fin or multiple fins on a bulk silicon substrate, [0023].
Ou further discloses The substrate 110 includes at least one anti-fuse region 110 a and at least one transistor region 110 b. An anti-fuse element (such as the anti-fuse element AF in FIG. 1B) will be formed on the anti-fuse region 110 a, and a transistor (such as the control transistor T in FIG. 1B) will be formed on the transistor region 110 b, [0028].
In FIGs. 9C, 9D, Ou discloses the anti-fuse region 110a or the at least one transistor region 110b includes:
a first fin (112);
a first gate structure (190a or 190b, [0040]) comprising a first gate dielectric layer (192) and a first gate layer (195, 196, [0040]), wherein the first gate dielectric layer covers a top surface and two lateral surfaces of a central region of the first fin (FIG. 9C shows the first gate dielectric layer 192 covers a top surface and two lateral surfaces of a central region of the first fin 112), the first gate dielectric layer is covered by the first gate layer (FIGs. 9C, 9D shows the first gate dielectric layer 192 is covered by the first gate layer 195, 196).
Ou further discloses source/drain regions 160 are formed in portions of the semiconductor fin 112, [0035].
Ou further discloses One advantage is that the anti-fuse element has a single breakdown mode (i.e., the fin-top mode) since the position design of the corresponding gate via. As such, the improved OTP devices have a well-known controlled cell characterization and good quality (reliability). Furthermore, the improved vertical distance between the gate via and the semiconductor fin provides good programming condition, [0061].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first antifuse transistor 230, the first select transistor 250, the first following transistor 240, and the second following transistor 220 each to have a fin and gate structure as taught by Ou in order to ensure the device is reliable and provides good programming condition as further taught by Ou. As a result, the first terminal 238 of the antifuse transistor would be a first terminal of a first fin, the second terminal 232 of the antifuse transistor would be a second terminal of the first fin, and the second drain/source terminal 234 would be electrically connected with the second terminal 232 of the first fin.
In the same field of endeavor, Liaw discloses:
fins of the third and fourth active area regions 151 and 161 are arranged along the X-direction, [0040].
Liaw further discloses the third active area region 151 comprises the four fins 152, 154, 156, 158, [0037].
Liaw further discloses In the example configuration in FIG. 3, a transistor may be formed by the gate electrode 172 and the third active area region 151. In some embodiments, such transistor having a gate, a drain, and a source is formed in the second circuit 104. The gate of the transistor is formed by the gate electrode 172. One of the drain or the source (referred to herein as “source/drain” or “S/D”) of the transistor is defined by a region of the third active area region 151 on one side (e.g., the upper side in FIG. 3) of the gate electrode 172. The other source/drain of the transistor is defined by another region of the third active area region 151 on the opposite side (e.g., the lower side in FIG. 3) of the gate electrode 172. For another example, a further transistor may be formed by the gate electrode 172 and the fourth active area region 161. In at least one embodiment, further transistors are formed by the gate electrode 170 and the corresponding third and fourth active area regions 151 and 161, [0041].
Liaw further discloses The contact areas 182, 184, 186, 188, 190, 192 are configured to electrically couple the underlying source/drains of the corresponding transistors with each other or with other circuitry of the semiconductor device 100, [0043]. Liaw discloses 182, 184, 186, 188, 190, 192 are contact plugs, [0065].
Liaw further discloses FinFET devices offer several advantages over traditional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices (also referred to as planar transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processing that is compatible with the fabrication processing of planar devices. Thus, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for a portion of, or the entire IC chip, [0023].
Accordingly, Liaw discloses in FIG. 3:
a first drain/source contact (182, 186, 190) layer electrically connected with the first terminal of the first fin (underlying source/drain region in 152, 154, 156, or 158, [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first antifuse transistor 230, the first select transistor 250, the first following transistor 240, and the second following transistor 220 each to have multiple fins with drain/source contact layers electrically connected with underlying source regions as taught by Liaw in order to obtain better chip area efficiency, and improve carrier mobility as further taught by Liaw. As a result, the first antifuse transistor 230 would have a first drain/source contact layer electrically connected with the first terminal/source/drain 238 of the first fin, wherein the first drain/source contact layer is connected with the second drain/source terminal 242 of the first following transistor 240 at least through the first terminal 238.
In the same field of endeavor, Chen discloses:
FIG. 1A is a schematic circuit diagram illustrating a conventional antifuse-type OTP memory cell, [0008].
Chen further discloses FIG. 2A is a schematic circuit diagram illustrating another conventional antifuse-type OTP memory cell, [0019].
In FIG. 2A, the antifuse-type OTP memory cell is configured by a first select transitor Ms, a first following transistor MFL, and an antifuse transistor MAF coupled in series.
Chen teaches As shown in FIG. 2A, the antifuse-type OTP memory cell 200 comprises a select transistor MS, a following transistor MFL and an antifuse transistor MAF. The first drain/source terminal of the select transistor MS is connected with a bit line BL. The gate terminal of the select transistor MS is connected with a word line WL. The second drain/source terminal of the select transistor MS is connected with the first drain/source terminal of the following transistor MFL. The gate terminal of the following transistor MFL is connected with a following control line FL. The second drain/source terminal of the following transistor MFL is connected with the first drain/source terminal of the antifuse transistor MAF. The gate terminal of the antifuse transistor MAF is connected with an antifuse control line AF, [0019].
Chen further teaches Please refer to FIG. 2B. When the program action is performed, the bit line BL receives a ground voltage (0V), the antifuse control line AF receives a program voltage VPP, the word line WL receives an on voltage VON, and the following control line FL receives a control voltage VFL. For example, the program voltage VPP is 5V, the on voltage VON is 1.8V, and the control voltage VFL is 1.8V. In response to the control voltage VFL, the following transistor MFL is controlled to be in a conducting state, [0022].
Chen further teaches When the select transistor MS is turned on and the following transistor MFL is in the conducting state, the ground voltage (0V) of the bit line BL is transferred to the first drain/source terminal of the antifuse transistor MAF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor MAF is equal to the program voltage VPP. Under this circumstance, a gate oxide layer of the antifuse transistor MAF is ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor MAF has a low resistance value. That is, the antifuse-type OTP memory cell 200 is in a low-resistance storage state, [0023].
As Liaw teaches that a gate dielectric layer includes an oxide, [0051], the gate oxide layer in Chen is understood as referring to a gate dielectric layer.
Chen further teaches As shown in FIG. 2D, the magnitude of the total leakage current generated by the antifuse-type OTP memory cell 200 is low, [0030].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the select transistor 250, the following transistor 240, and the antifuse transistor 230 as a memory cell wherein when a program action is performed, the first gate dielectric layer of the first antifuse transistor 230 is ruptured, so that the first memory cell 2001,1 is programmed into a low-resistance storage state as taught by Chen in order to result in a low total leakage current as further taught by Chen.
RE: Claim 2, Wu in view of Ou, Liaw, Chen discloses The antifuse-type memory as claimed in claim 1, wherein the first select transistor (From Wu FIG. 7: 250) comprises:
a third drain/source contact layer (From Liaw: a third drain/source contact layer 182, 186, or 190, [0043], [0065]) connected with the first bit line (As modified, Liaw’s third drain/source contact layer would overlap and electrically connect with Wu’s underlying source/drain 258 in FIG. 7, and would therefore be connected with the first bit line BL1);
a fourth drain/source contact layer (From Liaw FIG. 3: a fourth drain/source contact layer 182, 186, or 190, [0043], [0065]; As modified, Liaw’s fourth drain/source contact layer would overlap and electrically connect with Wu’s underlying source/drain 252);
a second fin (From Ou FIG. 9D: fin 112; As modified, Wu’s select transistor 250 has a second fin 112 from Ou FIG. 9D containing Wu’s source/drains 252, 254, 256, 258, [0049]), wherein a first terminal (From Wu FIG. 7: source or drain 258, [0052]) of the second fin is electrically connected with the third drain/source contact layer (As modified, Liaw’s third drain/source contact layer would be electrically connected with Wu’s first terminal 258 of the second fin), and a second terminal (252) of the second fin is electrically connected with the fourth drain/source contact layer (As modified, Liaw’s fourth drain/source contact layer would overlap and electrically connect with Wu’s 252); and
a second gate structure (As modified, Wu’s gate terminal 250G is modified to include Ou’s FIG. 9D gate structure 190b) comprising a second gate dielectric layer (Ou FIG. 9b: 192) and a second gate layer (Ou FIG. 9b: 195, 196, [0040]), wherein the second gate dielectric layer covers a top surface and two lateral surfaces of a central region of the second fin (In Ou FIG. 9D, the second gate dielectric layer 192 covers a top surface and two lateral surface of a central region of the second fin 112), the second gate dielectric layer is covered by the second gate layer (In Ou FIG. 9D, the second gate dielectric layer 192 is covered by the second gate layer 195, 196), and the second gate layer is connected with the first word line (As Wu’s gate terminal 250G of Wu’s first select transistor 250 in FIG. 7 is connected with the first word line WL1, [0026], [0047], the second gate layer of Wu’s 250G would be connected with the first word line WL1).
RE: Claim 3, Wu in view of Ou, Liaw, Chen discloses The antifuse-type memory as claimed in claim 2, wherein the first following transistor (From Wu FIG. 7: 240) comprises:
the fourth drain/source contact layer (Liaw’s fourth drain/source contact layer would be shared by Wu’s transistors 240 and 250 since Liaw teaches in FIG. 3, a source/contact layer 186 is shared by adjacent transistors since a first transistor defined by a region of 151 on the upper side of the gate 172, gate 172, and a region of 151 on the lower side of the gate 172, [0041]; a further transistor is formed by a region of 151 on the upper side of the gate 170, gate 170, and a region of 151 on a lower side of gate 170, [0041], [0043], [0065]; Accordingly, Wu’s following transistor 240 and select transistor 250 would share Liaw’s fourth drain/source contact layer);
the first drain/source contact layer (Since in Liaw FIG. 3, a source/contact layer 186 is shared by adjacent transistors, the first drain/source contact layer, which is electrically connected with Wu’s underlying source/drain 238 of the antifuse transistor 230, would be shared between Wu’s antifuse transistor 230 and following transistor 240);
a third fin (From Ou FIG. 9D: fin 112; As modified, Wu’s following transistor 240 has a third fin 112 from Ou FIG. 9D containing its source/drains 242, 244, 246, 248), wherein a first terminal (248) of the third fin is electrically connected with the fourth drain/source contact layer (As the fourth drain/source contact layer is shared between transistors 240, 250, it would be electrically connected with source/drains 248, 252), and a second terminal (242) of the third fin is electrically connected with the first drain/source contact layer (As the first drain/source contact is shared between transistors 240, 230, it would be electrically connected with source/drains 238, 242); and
a third gate structure (As modified, Wu’s gate terminal 240G is modified to include Ou’s FIG. 9D gate structure 190b) comprising a third gate dielectric layer (Ou FIG. 9b: 192) and a third gate layer (Ou FIG. 9b: 195, 196, [0040]), wherein the third gate dielectric layer covers a top surface and two lateral surfaces of a central region of the third fin (In Ou FIG. 9D, the third gate dielectric layer 192 covers a top surface and two lateral surfaces of a central region of the third fin 112), the third gate dielectric layer is covered by the third gate layer (In Ou FIG. 9D, the third gate dielectric layer 192 is covered by the third gate layer 195, 196), and the third gate layer is connected with the first following control line (As Wu’s gate terminal 240G of 240 is connected to the following control line FL, [0026], [0048], the third gate layer of Wu’s 240G would be connected to the following control line FL).
RE: Claim 4, Wu in view of Ou, Liaw, Chen discloses The antifuse-type memory as claimed in claim 3, wherein the antifuse-type memory further comprises a FinFET transistor (From Wu FIG. 7: 220; As modified, 220 has a fin structure as modified by Ou; Ou teaches embodiments are discussed below in the context of forming finFET transistors having a single fin or multiple fins, [0023]), and the FinFET transistor comprises:
the second drain/source contact layer (From Liaw FIG. 3: a second drain/source contact layer 182, 186, or 190, [0043], [0065]; As modified, Liaw’s second drain/source contact layer would overlap and electrically connect with Wu’s underlying source/drain 228);
a fifth drain/source contact layer (From Liaw: a fifth drain/source contact layer 182, 186, or 190, [0043], [0065]; As modified, Liaw’s fifth drain/source contact layer would overlap and electrically connect with Wu’s underlying source/drain 222);
a fourth fin (From Ou FIG. 9D: fin 112; As modified, Wu’s transistor 220 has a fourth fin from Ou FIG. 9D containing its source/drains 222, 224, 226, 228, [0046]), wherein a first terminal (228) of the fourth fin is electrically connected with the second drain/source contact layer, and a second terminal (222) of the fourth fin is electrically connected with the fifth drain/source contact layer; and
a fourth gate structure (As modified, Wu’s gate terminal 220G is modified to include Ou’s FIG. 9D gate structure 190b) comprising a fourth gate dielectric layer (Ou FIG. 9b: 192) and a fourth gate layer (Ou FIG. 9b: 195, 196, [0040]), wherein the fourth gate dielectric layer covers a top surface and two lateral surfaces of a central region of the fourth fin (In Ou FIG. 9D, the fourth gate dielectric layer 192 covers a top surface and two lateral surface of a central region of the fourth fin 112), and the fourth gate dielectric layer is covered by the fourth gate layer (In Ou FIG. 9D, the fourth gate dielectric layer 192 is covered by the fourth gate layer 195, 196).
Wu in view of Ou, Liaw, Chen does not explicitly disclose:
the FinFET transistor (220) is a dummy FinFET transistor.
However, as stated in MPEP 2114, "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.
Accordingly, though the transistor 220 is not disclosed as being operated as a dummy transistor, it meets all the structural limitations of the claimed dummy transistor and therefore the claimed dummy transistor is not differentiated from the transistor 220 as modified.
RE: Claim 6, Wu in view of Ou, Liaw, Chen discloses The antifuse-type memory as claimed in claim 1, wherein the first bit line receives the ground voltage, the first word line receives an off voltage, the first following control line receives the conducting voltage and the first antifuse control line receives the program voltage when the program action is performed, the first gate dielectric layer of the first antifuse transistor is not ruptured, so that the first memory cell is programmed into a high-resistance storage state (Chen teaches When the program inhibition action is performed, the bit line BL receives the ground voltage (0V), the antifuse control line AF receives the program voltage VPP, the word line WL receives an off voltage VOFF, and the following control line FL receives a control voltage VFL. For example, the off voltage VOFF is 0V, [0024]; Chen teaches when the select transistor MS is turned off and the following transistor MFS is in the conducting state, the ground voltage (0V) of the bit line BL cannot be transferred to the first drain/source terminal of the antifuse transistor MAF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor MAF is very low. Under this circumstance, the gate oxide layer of the antifuse transistor MAF is not ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor MAF is maintained at a high resistance value. That is, the antifuse-type OTP memory cell 200 is in a high-resistance storage state, [0025]).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ou, Liaw, Chen as applied to claim 6 above, and further in view of CN111554684A (“Yongxiang”).
RE: Claim 7, Wu in view of Ou, Liaw, Chen does not explicitly disclose The antifuse-type memory as claimed in claim 6, wherein when a read action is performed, the first bit line receives the ground voltage, the first word line receives the on voltage, the first following control line receives the conducting voltage and the first antifuse control line receives a read voltage, so that the first memory cell generates a read current to the first bit line, wherein a storage state of the memory cell is determined as the high-resistance storage state or the low-resistance storage state according to a magnitude of read current.
However, in the same field of endeavor, Yongxiang teaches:
In the read operation (Read), the word line WL receives the third turn-on voltage Von3, the follow line FL receives the fourth turn-on voltage Von4, the bit line BL receives the ground voltage 0V, and the anti-fuse control line AF receives the read voltage Vr, pg. 18, lines 1-6.
Yongxiang teaches that the read current is generated to the Bit line BL, pg. 14, lines 4-9.
Yongxiang teaches the storage state of the non-volatile memory can be determined based on the magnitude of the reading current generated by the non-volatile memory. For example, a reference current Iref is provided, the magnitude of which is between the first read current Ir1 and the second read current Ir2. When the read current is greater than the reference current Iref, it is determined that the non-volatile memory is in the low resistance state, and it is confirmed that the non-volatile memory is in the first storage state (for example, "1"). In addition, when the read current is less than the reference current Iref, it is determined that the non-volatile memory is in the high resistance state, and it is confirmed that the non-volatile memory is in the second storage state (for example, "0"), pg. 14, lines 14-22.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform a read operation as taught by Yongxiang in order to read data stored by the memory cell 2001,1.
RE: Claim 8, Wu in view of Ou, Liaw, Chen, Yongxiang discloses The antifuse-type memory as claimed in claim 7, wherein if the read current is lower than a reference current, the first memory cell is in the high-resistance storage state, wherein if the read current is higher than the reference current, the first memory cell is in the low-resistance storage state (Yongxiang teaches the storage state of the non-volatile memory can be determined based on the magnitude of the reading current generated by the non-volatile memory. For example, a reference current Iref is provided, the magnitude of which is between the first read current Ir1 and the second read current Ir2. When the read current is greater than the reference current Iref, it is determined that the non-volatile memory is in the low resistance state, and it is confirmed that the non-volatile memory is in the first storage state (for example, "1"). In addition, when the read current is less than the reference current Iref, it is determined that the non-volatile memory is in the high resistance state, and it is confirmed that the non-volatile memory is in the second storage state (for example, "0"), pg. 14, lines 14-22).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ou, Liaw, Chen as applied to as applied to claim 1 above, and further in view of US20200295004 A1 (“Kim”), further in view of US 20200287019 A1 (“Mulfinger”).
RE: Claim 9, Wu in view of Ou, Liaw, Chen discloses The antifuse-type memory as claimed in claim 1, wherein the semiconductor substrate comprises a well structure (160 in Liaw FIG. 3 or 5; Liaw teaches the third active area region 151 is within a well region 150 which is an n-well region in one or more embodiments, and the fourth active area region 161 is within a well region 160 which is a p-well region in one or more embodiments, [0036]; FIGs. 3, 5 show the fins/active regions 161 constructed over a p-type region 160; Liaw teaches Example materials of the third and fourth active area regions 151 and 161 include, but are not limited to, semiconductor materials doped with various types of p-dopants and/or n-dopants, [0036]; Accordingly, before the effective filing date of the claimed invention, there was a need to determine the conductivity of the well region; It would have been obvious to form the fins/active regions of the first select transistor, the first following transistor, the first antifuse transistor over a p-type well region as this would have been obvious to try since a p-type well region is one solution for the well region over which the fins of transistors are formed, and this would have had a reasonable expectation of success, see MPEP 2143), and the well structure comprises a first type region (160); wherein the first select transistor, the first following transistor, the first antifuse transistor are constructed over the first type region (As modified, the fins of the first select transistor, the first following transistor, the first antifuse transistor are constructed over Liaw’s p-type well region 160).
Wu in view of Ou, Liaw, Chen does not explicitly disclose:
the well structure comprises a second type region, wherein a lateral side and a bottom side of the first type region are contacted with the second type region, and the lateral sides and the bottom side of the first type region are enclosed by the second type region.
In the same field of endeavor, Kim discloses in FIGs. 2-4:
wherein a semiconductor substrate (102A in FIG. 4, [0019]) comprises a well structure (122, 123P, 128, 120 in FIG. 4, [0016], [0022], [0023], [0033]); and
the well structure comprises a first type region (128; 128 is a P-well, [0016]) and a second type region (120, 122; 122 is an N-well region, [0023]; 120 is a deep N-well region, [0023]), wherein a lateral side and a bottom side of the first type region are contacted with the second type region (FIG. 4 shows a bottom side of 128 is in contact with 120; In the same field of endeavor, Mulfinger discloses A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or “in direct contact with” another feature if intervening features are absent. A feature may be “indirectly on” or “in indirect contact with” another feature if at least one intervening feature is present, [0040]; Accordingly, under a broad reasonable interpretation, a lateral side of 128 is in indirect contact with 122 through 130 in FIG. 4), and the lateral sides and the bottom side of the first type region are enclosed by the second type region (ring-like N-well region 122 effectively surrounds the collective outer perimeter of the first isolated P-well 126 and the second isolated P-well 128, [0023]; FIGs. 2-4 show 120, 122 enclose 128).
Kim further discloses application of a biasing voltage of −Vdd to the first isolated P-well 126 will forward bias the PFET transistor 10, thereby making the PFET transistor 10 exhibit a relatively higher leakage current and operate at a relatively higher switching speed as compared to those performance metrics of the PFET transistor 10 without −Vdd body-biasing, because the PFET region 103 has more positive charges than the positive charges in P-well 126, [0017].
Kim further discloses a biasing voltage in the range of +Vdd to −Vdd may be applied independently to each of the isolated and separate P- wells 126, 128 on an as-needed basis so as to modify the performance characteristics of one or more of the transistors, [0036].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate to include the P-well 128, ohmic contact region 123P, N well 122, and deep N well 120 as taught by Kim in order to modify the performance characteristics of the transistors.
RE: Claim 10, Wu in view of Ou, Liaw, Chen, Kim, Mulfinger discloses The antifuse-type memory as claimed in claim 9, wherein the first type region is a P-type region (From Kim FIGs. 2-4: 128; 128 is a P-well, [0016]), and the second type region is an N-type region (120, 122; 122 is an N-well region, [0023]; 120 is a deep N-well region, [0023]), wherein the P-type region is a P-well region (128; 128 is a P-well, [0016]), and the N-type region comprises a deep N-well region (120) and a pickup N-well region (122), wherein the pickup N-well region surrounds the P-well region (ring-like N-well region 122 effectively surrounds the collective outer perimeter of the first isolated P-well 126 and the second isolated P-well 128, [0023]; FIGs. 2-4 show 122 surrounding 128), a top side of the pickup N-well region is exposed to a surface of the semiconductor substrate (Kim FIG. 4 shows top side of 122 is exposed from upper surface of upper left portion of 102A that excludes 122), a bottom side of the pickup N-well region is contacted with the deep N-well region (FIG. 4 shows a bottom side of the pickup N-well region 122 is contacted with the deep N-well region 120), the lateral side of the P-well region is contacted with the pickup N-well region (FIG. 4 shows the lateral left side of the P-well region 128 is in indirect contact with the pickup N-well region 122 through 130), and a bottom side of the P-well region is contacted with the deep N-well region (FIG. 4 shows a bottom side of the P-well region 128 is contacted with the deep N-well region 120).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ou, Liaw, Chen, Kim, Mulfinger as applied to as applied to claim 9 above, and further in view of US 5825600 A (“Watt”).
RE: Claim 11, Wu in view of Ou, Liaw, Chen, Kim, Mulfinger discloses The antifuse-type memory as claimed in claim 9, wherein the first type region is a P-type region (128; 128 is a P-well, [0016]), and the second type region is an N-type region (120, 122; 122 is an N-well region, [0023]; 120 is a deep N-well region, [0023]), wherein the P-type region comprises a deep P-well region (128; 128 is a P-well, [0016]), and the N-type region comprises an N buried region (120) and a pickup N-well region (122)the pickup N-well region surrounds the deep P-well region (a ring-like N-well region 122 that effectively surrounds the collective outer perimeter of the first isolated P-well 126 and the second isolated P-well 128, [0023]), a top side of the pickup N-well region is exposed to a surface of the semiconductor substrate (Kim FIG. 4 shows top side of 122 is exposed from upper surface of upper left portion of 102A that excludes 122), a bottom side of the pickup N-well region is contacted with the N buried region (FIG. 4 shows a bottom side of the pickup N-well region 122 is contacted with the N buried region 120).
Wu in view of Ou, Liaw, Chen, Kim, Mulfinger does not explicitly disclose:
wherein the P-type region comprises a P-well region and the deep P-well region;
wherein a bottom side of the P-well region is contacted with the deep P-well region;
the pickup N-well region surrounds the P-well region and the deep P-well region;
a lateral side of the P-well region and a lateral side of the deep P-well region are contacted with the pickup N-well region, and a bottom side of the P-well region is contacted with the N buried region.
However, in a similar field of endeavor, Watt discloses:
a well region of a second conductivity type opposite said first conductivity type formed in said substrate, said well region including a first ohmic contact region of said second conductivity type formed in said well, see claim 19.
Accordingly, before the effective filing date of the claimed invention, there was a need to determine the conductivity type of the ohmic contact region 123P in relation to the conductivity type of the well region 128.
In Kim FIG. 4, the ohmic region 123P is in the well region 128.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conductivity type of the ohmic contact region 123P to be the same as the well region 128, which is P-type, as this would have been obvious to try since the same conductivity type is one solution for the conductivity type of an ohmic contact region and well region identified by Watt, and this would have had a reasonable expectation of success, see MPEP 2143.
As modified:
the P-type region (From Kim FIG. 4: 128, 123P) comprises a P-well region (123P) and the deep P-well region (128, which extends to a deeper level than 123P in FIG. 4);
wherein a bottom side of the P-well region is contacted with the deep P-well region (FIG. 4 shows a bottom side of the P-well region 123P is contacted with the deep P-well region 128);
the pickup N-well region (122) surrounds the P-well region and the deep P-well region (FIGs. 3, 4 show 122 surrounding 128; As 123P is positioned within 128, 122 would surround 123P);
a lateral side of the P-well region and a lateral side of the deep P-well region are contacted with the pickup N-well region (FIG. 4 shows a lateral side of the P-well region 123P is in indirect contact with 122 through 128, 130; FIG. 4 shows a lateral side of the deep P-well region 128 is in indirect contact with the pickup N-well region 122 through 130), and
a bottom side of the P-well region is contacted with the N buried region (FIG. 4 shows a bottom side of the P-well region 123P is in indirect contact with the N buried region 120 through 128).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ou, Liaw, Chen as applied to as applied to claim 1 above, and further in view of US20190109040A1 (“Chao”).
RE: Claim 12. Wu in view of Ou, Liaw, Chen does not explicitly disclose The antifuse-type memory as claimed in claim 1, wherein the semiconductor substrate receives a substrate voltage with a negative voltage value.
However, in the same field of endeavor, Chao discloses:
illustrative embodiments are described using a multi-channel GAA finFET, [0039].
Chao further teaches When voltage Vsub is applied to substrate 320, the current flow between epi 304 and epi 306, through channels 314-318, switches from value A to value B. A lower (negative) value Vsub=0 plot shows a less distinct switch or change in the current value, as compared to the plots for Vsub=−1, Vsub=−2, Vsub=−3, and Vsub=−4 which show more pronounced switches from A to B. Thus, the higher the negative voltage of substrate 320 (to draw electrons away from substrate 320), the better the performance of the GAA device in view 332, [0077].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate to receive a negative voltage as taught by Chao in order improve performance of the FinFETs 230, 240, 250 as further taught by Chao.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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