DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/22/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: QUANTUM DEVICE COMPRISING INTEGRATED CONDUCTOR PATTERN AND METHOD OF MANUFACTURING SAME
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the surface of the wiring component” in line 4 and “the wiring layer of the laminated substrate" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of a surface of the wiring component and a wiring layer of the laminated substrate. For proper antecedence and for examination purposes, the limitations are interpreted as “a surface of the wiring component” and “ a wiring layer of the laminated substrate”, respectively. Appropriate correction is required. Claims 2-14 are also rejected under 35 U.S.C. 112(b) as being indefinite for further limiting and dependent on indefinite claim 1. Claim 4 recites the limitation "the surface of the laminated substrate” in line 2. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of a surface of the laminated substrate. For proper antecedence and for examination purposes, the limitation is being interpreted as "a surface of the laminated substrate.” Appropriate correction is required.
Claim 8 recites the limitation "the single wiring component” in line 2. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of a single wiring component previously in the claim. For proper antecedence and for examination purposes, the limitation is being interpreted as “a single wiring component.” Appropriate correction is required. Claim 15 recites the limitation "the surface of the wiring component” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of a surface of the wiring component in the claims. For proper antecedence and for examination purposes, the limitation is being interpreted as “a surface of the wiring component.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, 9, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nanba et al. US PGPub. 2021/0407928 in view of Autry et al. US Pat. 12,456,616. Regarding claim 1, Nanba teaches a quantum device (100, fig. 1 and 9) [0026] using a quantum state (vacuum state [0061] which is a quantum state containing the lowest possible energy), comprising: a quantum chip (111, fig. 1) [0043]; a wiring component (interposer 112 of fig. 1 being substituted with interposer 212 of fig. 9; hereinafter will use 112 and 212 interchangeably depending on which figure portrays the item better) [0043] having a wiring layer (212,b, 212c, fig. 9) [0067]; a laminated substrate (128+127, fig. 1) [0053] installed so that at least the (top) surface of the wiring component (112) on which the quantum chip (111) is mounted is exposed; and a wire bond (126, fig. 1) [0053] connecting the wiring layer (127, fig. 1) [0053] of the laminated substrate (128+127) with the wiring layer (112c) of the wiring component (112) (Nanba et al., fig. 1). But Nanba fails to teach wherein the wire bond is an integrated conductor pattern or fails to teach an integrated conductor pattern connecting the wiring layer (127) of the laminated substrate (128+127) with the wiring layer (112c) of the wiring component (112). However, Autry teaches a quantum device (col. 11, lines 48-49) where electrical connections are made between bond pads and an external circuit using wire bonds or patterned electrically conductive films (Autry et al, (col. 32, lines 15-18)). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitution of the wire bond of Nanba with the patterned electrically conductive films as taught by Autry because wire bonds and patterned electrically conductive films are is well known in the art as alternatives (col. 32, lines 15-18) and such substitution is art recognized equivalence for the same purpose (for making excellent electrical connections) to obtain predictable results (see MPEP 2144.06).
Regarding claim 2, Nanba in view of Autry teaches the quantum device according to claim 1, wherein the wiring component (12) is embedded in the laminated substrate (127+128) (Nanba et al., fig. 1).
Regarding claim 5, Nanba in view of Autry teaches the quantum device according to claim 1, further comprising the wiring component (212, fig. 9) having a plurality of the wiring layers (212c and 212b, fig. 9) [0067] (Nanba et al., fig. 9, [0067]).
Regarding claim 6, Nanba in view of Autry teaches he quantum device according to claim 1, wherein the wiring component (212) includes a core material (212a, fig. 9) [0067] and a through-via (212d, fig. 9) [0067] that penetrates the core material (212a) (Nanba et al., fig. 9, [0067]).
Regarding claim 9, Nanba in view of Autry teaches the quantum device according to claim 1, wherein all or part of the quantum chip (111) is arranged to overlap (fig. 2) the wiring component (112) in plan view (Nanba et al., fig. 1-2).
Regarding claim 11, Nanba teaches the quantum device according to claim 1, wherein the laminated substrate (127+128) has a plurality of wiring layers (127, fig. 1) [0053]).
Regarding claim 15, Nanba teaches a method of manufacturing a quantum device (100, fig. 1 and 9) [0026] comprising a quantum chip (111, fig. 1) [0043], a wiring component (interposer 112 of fig. 1) [0043] having a wiring layer (112c, 112b, fig. 1) [0045], and a laminated substrate (interposer 112 of fig. 1) [0053] installed so that at least the surface of the wiring component (112) on which the quantum chip (111) is mounted is exposed, the method comprising: embedding the wiring component (112) in a recess (hereinafter called 128’, fig. 1) of the laminated substrate (128+127); and connecting the laminated substrate (127+128) and the wiring component (112) by a wire bond (126, fig. 1) [0053] (Nanba et al., fig. 1). But Nanba fails to teach wherein the wire bond is an integrated conductor pattern or connecting the laminated substrate (128+127) and the wiring component (112) by an integrated conductor pattern. However, Autry teaches a quantum device (col. 11, lines 48-49) where electrical connections are made between bond pads and an external circuit using wire bonds or patterned electrically conductive films (Autry et al, (col. 32, lines 15-18)). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitution of the wire bond of Nanba with the patterned electrically conductive films as taught by Autry because wire bonds and patterned electrically conductive films are is well known in the art as alternatives (col. 32, lines 15-18) and such substitution is art recognized equivalence for the same purpose (for making excellent electrical connections) to obtain predictable results (see MPEP 2144.06).
Allowable Subject Matter
Claims 3-4, 7-8, 10 and 12-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a quantum device comprising “a relief portion at at least either one of an outer surface corner between one outer surface of the wiring component and another outer surface that intersects that one outer surface, and an inner surface corner between one inner surface of the laminated substrate and another inner surface that intersects that one inner surface” as recited in claim 3 in combination with the rest of the limitations as recited in claims 1-2; a quantum device wherein “the conductor pattern includes a portion of a conductor layer on a surface of the laminated substrate” as recited in claim 4 in combination with the rest of the limitations of claim 1;
a quantum device wherein “the wiring component includes a plurality of divided wiring components arranged on the laminated substrate, and the quantum chip is arranged across the divided wiring components” as recited in claim 7 in combination with the rest of the limitations of claim 1; a quantum device wherein “a plurality of the quantum chips are arranged on a single wiring component” as recited in claim 8 in combination with the rest of the limitations of claim 1; a quantum device wherein “the quantum chip is arranged so as to overlap a plurality of the wiring components in plan view” as recited in claim 10 in combination with the rest of the limitations of claim 1; a quantum device wherein “an insulating layer of the laminated substrate is composed of organic materials” as recited in claim 12 in combination with the rest of the limitations of claim 1; and a quantum device wherein “the laminated substrate is provided with a connector” as recited in claim 13 in combination with the rest of the limitations of claim 1. Claim 14 is also objected to as allowable for further limiting and depending upon allowable claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kikuchi et al. US PGPub. 2021/0399195 (fig. 7) and Nanba et al. US PGPub. 2021/0399193 (fig. 6) and 2021/0399194 (fig. 1) all teach a quantum device comprising a quantum chip on a wiring component.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NDUKA E OJEH/Primary Examiner, Art Unit 2892
Prosecution Insights