DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-16 and 18-20 are rejected under 35 U.S.C. 102(a)()1) as being anticipated by Shivaraman et al. (20220199635).
1. A memory device comprising: a substrate; a plurality of bit lines on the substrate and extending in a first horizontal direction and separated from each other in a second horizontal direction that intersects the first horizontal direction; a plurality of channel layers extending in a vertical direction that is perpendicular to an upper surface of the substrate on the plurality of bit lines; a plurality of word lines on a bit line among the plurality of bit lines in the vertical direction, extending in the second horizontal direction, and separated from each other in the first horizontal direction; an interlayer insulating layer between the plurality of channel layers; a gate insulating layer between a channel layer among the plurality of channel layers and a word line among the plurality of word lines and on an upper surface of the interlayer insulating layer opposite the substrate (see paragraphs 0037, 0043 and 0062); and a ferroelectric capacitor structure on the channel layer in the vertical direction and comprising a plurality of first electrodes separated from each other in the vertical direction (see Figs. 5A-5G, elements 102/124).
Regarding Claim 2, an etching stop layer on the channel layer, the interlayer insulating layer, and the gate insulating layer (see paragraphs 0033-0037, 0043, 0062)
Regarding Claim 4, in paragraph 0035, the ferroelectric capacitor structure further comprises: a second electrode penetrating the plurality of first electrodes in the vertical direction; and a dielectric layer extending around the second electrode and between each of the plurality of first electrodes and the second electrode.
Regarding Claim 5, in Figs. 1B, 1C, 3A, 3C and 3E, the second electrode has a cylindrical shape.
Regarding Claim 6, in Figs. 1A, 1B, 1C, 3A, 3C and 3E, the dielectric layer has a hollow cylindrical shape, and an outer diameter of the dielectric layer is less than a width of the channel layer in the first horizontal direction or the second horizontal direction.
Regarding Claim 7, in Figs. 1A and 5G, a cross-section of the gate insulating layer, in a direction perpendicular to the second horizontal direction, has an upside-down U shape.
Regarding Claim 8, in Figs 1A and 5G, wherein the gate insulating layer extends on a first sidewall of the channel layer extending in the first horizontal direction, and wherein the gate insulating layer is not contact with a second sidewall of the channel layer extending in the second horizontal direction.
Regarding Claim 9, in Figs. 1A and 5G, an upper surface of the gate insulating layer, which is opposite the substrate, is coplanar with an upper surface of each of the plurality of channel layers.
Regarding Claim 10, in Figs. 1A and 5G, wherein the gate insulating layer and each of the plurality of channel layers are in contact with the bit line, and wherein a surface of the gate insulating layer in contact with the bit line is coplanar with a surface of each of the plurality of channel layers in contact with the bit line.
Regarding Claim 11, in Figs 1A and 5A-5G and paragraphs 0037, 0043 and 0062, elements 102/124, Shivaraman et al. discloses a memory device comprising: a substrate; a plurality of bit lines on the substrate and extending in a first horizontal direction and separated from each other in a second horizontal direction that intersects the first horizontal direction; a plurality of vertical transistors each comprising word lines on the plurality of bit lines in a vertical direction that is perpendicular to the substrate, wherein the word lines extend in the second horizontal direction and are separated from each other in the first horizontal direction, a channel layer extending in the vertical direction on the substrate, and a gate insulating layer between one of the word lines and the channel layer; an interlayer insulating layer between the plurality of vertical transistors; an etching stop layer on the gate insulating layer and the interlayer insulating layer; and a ferroelectric capacitor structure on each of the plurality of vertical transistors in the vertical direction and comprising two or more capacitors, wherein the gate insulating layer extends along an upper surface of the interlayer insulating layer and on an upper surface of the one of the word lines opposite the substrate.
Regarding Claim 12, in Figs 1A and 5A-5G, the ferroelectric capacitor structure comprises: two or more first electrodes stacked on the etching stop layer and separated from each other in the vertical direction; a second electrode penetrating the two or more first electrodes in the vertical direction; and a ferroelectric layer extending around the second electrode and between each of the two or more first electrodes and the second electrode.
Regarding Claim 13, in paragraphs 0033-0037, 0043, 0062, the channel layer comprises: a first surface in contact with one of the bit lines; and a second surface opposite to the first surface and in contact with the second electrode, wherein the second surface is in contact with the etching stop layer and the ferroelectric layer.
Regarding Claim 14, in paragraphs 0033-0037, 0043, 0062, wherein the channel layer comprises: a first surface in contact with one of the bit lines; and a second surface opposite to the first surface and in contact with the second electrode, wherein the second surface is not in contact with the ferroelectric layer.
Regarding Claim 15, in paragraphs 0033-0037, 0043, 0062, wherein each of a width of the channel layer in the first horizontal direction and a width of the channel layer in the second horizontal direction is substantially equal to a diameter of the second electrode.
Regarding Claim 16, in paragraphs 0033-0037, 0043, 0062, respective widths of the channel layer in the first horizontal direction and in the second horizontal direction decrease in the vertical direction toward the ferroelectric capacitor structure.
Regarding Claim 18, in Figs. 1A and 5A-5G and paragraphs 0033-0037, 0043, 0062, elements 102/124, Shivraman et al. discloses a memory device comprising: a substrate; a first interlayer insulating layer on the substrate; a plurality of bit lines buried in the first interlayer insulating layer, extending in a first horizontal direction, and separated from each other in a second horizontal direction that intersects the first horizontal direction; a plurality of vertical transistors comprising a plurality of channel layers extending in a vertical direction on a bit line among the plurality of bit lines, a word line separated from the plurality of channel layers in the first horizontal direction and extending in the second horizontal direction, and a gate insulating layer between each of the plurality of channel layers and the word line and extending along a sidewall of each of the plurality of channel layers; a second interlayer insulating layer between the plurality of vertical transistors on the bit line; an etching stop layer on the gate insulating layer and the second interlayer insulating layer; and a plurality of ferroelectric capacitor structures on the plurality of vertical transistors in the vertical direction, and each of the plurality of ferroelectric capacitor structures comprising a plurality of first electrodes stacked on and separated from each other on the second interlayer insulating layer in the vertical direction, a hollow ferroelectric layer conformally extending along a sidewall of a hole penetrating the plurality of first electrodes in the vertical direction, and a second electrode extending in the vertical direction inside the hollow ferroelectric layer, wherein the gate insulating layer has a first surface in contact with the bit line and a second surface opposite to the first surface and in contact with the etching stop layer, the second surface longitudinally extends the second horizontal direction, and the second surface overlaps, in the vertical direction, the plurality of vertical transistors separated from each other in the second horizontal direction.
Regarding Claim 19, in Figs. 1A and 5A-5G, a cross-section of the gate insulating layer, in a direction perpendicular to the second horizontal direction, has an upside-down U shape.
Regarding Claim 20, in Figs. 1A and 5A-5G, wherein the sidewall of each of the plurality of channel layers is a first sidewall and each of the plurality of channel layers comprises a second sidewall, wherein the gate insulating layer extends on the first sidewall, which extends in the first horizontal direction, and wherein the gate insulating layer is not contact with the second sidewall, which extends in the second horizontal direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable Shivaraman et al. (20220199635) in view of Young et al. (20210408022)
Regarding Claims 3 and 17, Shivaraman et al. discloses everything except to disclose the required monocrystalline silicon channel structure. However, Young et al. discloses a ferroelectric memory structure where in paragraphs 0017 and 0071 the required monocrystalline channel structure is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required monocrystalline channel structure for high speed purposes.
Examiner is including Dutta, (20240114694), Haratipour (20220208777), Haratipour (20220208778), Ramaswamy (20200111800) and Peng 20160118404 (particularly see paragraphs 0031, 0038 and 0040 for single crystal silicon channel) as pertinent prior art references that are NOT relied upon but that do disclose FeRAM/FRAM devices with channel structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/26/2026
