DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1 and 17 are objected to because of the following informalities:
Claim 1 recites “a bit line shield structure on the lower circuit pattern, the bit line shield structure including an opening extending therethrough”, which would render the claim indefinite in that it is unclear whether the scope of the claim encompasses an opening through the bit line shield or the lower circuit pattern. However, the recitation of “the opening extending through the bit line shield structure” later in the claim indicates the case is likely the former. Nevertheless, the initial recitation of “a bit line shield structure on the lower circuit pattern, the bit line shield structure including an opening extending therethrough” introduces ambiguity which should be avoided in the first place.
Claim 17 recites “first and second bonding layers”, which would render the claim indefinite in that it is unclear whether a plurality of first bonding layers and a plurality of second bonding layers or a singular first bonding layer and singular second bonding layer is being claimed. However, the recitation of “the second bonding layer” in the singular later in the claim indicates the case is likely the latter. Nevertheless, the initial recitation of “first and second bonding layers” introduces ambiguity which should be avoided in the first place.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11, the claim recites “channels on the bit line structures, respectively”. This limitation can be interpreted in multiple mutually-exclusive ways, rendering the broadest reasonable interpretation of the claim and its scope indefinite. Depending upon interpretation, the limitation may take on any of the following mutually-exclusive meanings: a) on each of the bit line structures is a plurality of channels; or b) on each of the bit line structures at least one channel, together being a plurality of channels. For the purpose of examination, Examiner interprets the limitation according to interpretation b), the limitation reading “a plurality of channels, wherein at least one channel of the plurality of channels is on each of the bit line structures, respectively”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 11581317 B2, hereinafter T1), and further in view of Lee et al. (US 20210225758 A1, hereinafter L1).
Regarding independent claim 11, T1 discloses in T1 FIG. 22A-22C, and 23-24 and associated text A semiconductor device comprising: a bit line shield structure on a substrate (reference structure 90 and shield lines 66, together comprising a bit line shield structure, are in memory array 98, which is tier 2 (170) in T1 FIG. 24, which is on the control circuitry tier 1 (168), which is supported by (read “on”) a substrate (T1 (115)), therefore 66/90 is on a substrate), the bit line shield structure comprising: a bit line shield plate having a planar surface extending in first and second directions that are substantially parallel to an upper surface of the substrate (reference structure 90, considered a bit line shield plate, extends in the x- and y-directions, as shown in T1 FIG. 22A and 22B, respectively, is planar, and parallel to the bottom surface of 168/tier 1, which would correspond with the upper surface of the substrate, which is not shown); and bit line shield fins spaced apart from each other in the first direction on the bit line shield plate, each of the bit line shield fins protruding from the bit line shield plate in a vertical direction substantially perpendicular to the upper surface of the substrate and extending in the second direction, the first and second directions intersecting each other (conductive shield material 44 of the shield 66/90 protrude in the z-direction, extend in the y-direction, and are spaced apart in the x-direction, as shown; the z-direction is perpendicular to the substrate, as interpreted, and the x- and y-directions intersect one another as coordinate axes); bit line structures on the bit line shield plate between respective pairs of the bit line shield fins, each of the bit line structures extending in the second direction (any of digit lines DL1-DL4 – interpreted as bit lines – on 90, which extend in the y-direction); a plurality of channels, wherein at least one channel of the plurality of channels is on each of the bit line structures, respectively (channel regions 84 on each of DL1-DL4); and capacitors on and electrically connected to the channels, respectively (storage elements 94 are capacitors as shown in T1 FIG. 23 and stated in T1 (111), which are connected to respective channel regions 84 by source/drain regions 80).
T1 does not explicitly disclose the bit line shield plate includes openings therethrough, each of the bit line structures overlapping at least one of the openings in the vertical direction.
However, in the same field of endeavor, L1 discloses in L1 FIG. 4 and associated text the bit line shield plate includes openings therethrough (shielding pattern 160 has gaps corresponding to 175B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the bit line shield openings and corresponding structures of L1 with the device of T1 such that each of the bit line structures overlapping at least one of the openings in the vertical direction to provide functional through-vias from the bit line to underlying structures with reduced resistance and coupling noise (L1 [0093]).
Regarding dependent claim 12, T1, as modified by L1, further discloses in L1 FIG. 5B and associated text The semiconductor device according to claim 11, wherein the openings are spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate, the third direction defining an acute angle with respect to the first and second directions (please refer to the annotated L1 FIG. 5B below).
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Regarding dependent claim 13, T1, as modified by L1, further discloses in L1 FIG. 5B and associated text The semiconductor device according to claim 11, wherein each of the openings extends in a third direction substantially parallel to the upper surface of the substrate, the third direction defining an acute angle with respect to the first and second directions (please refer to the annotated L1 FIG. 5B above).
Regarding dependent claim 14, T1, as modified by L1, further discloses in L1 FIG. 5A-5B and associated text The semiconductor device according to claim 2, wherein the openings are spaced apart from each other in the first direction (openings corresponding to plugs 175B and 175A are spaced apart in a direction – corresponding to the first direction in that it is the direction in which bit lines 143B are spaced apart in L1 FIG. 5A), and each of the openings extends in the second direction (the openings extend in a direction perpendicular to the first direction as interpreted, corresponding to the second direction; see also the annotated L1 FIG. 5B above, where the second direction as interpreted is labeled as D2).
Additionally, if not explicitly disclosed by L1, which the examiner does not concede, the references as combined would have this claimed structure, since one of ordinary skill in the art before the effective filing date of the invention would be motivated to combine the references such that each of the bit/digit lines DL1-DL4 of T1 could be read by connections through the holes of L1 to lower circuit patterns of M1, by the same motivation for providing such a connection to an individual bit/digit line, providing each digit line with a corresponding hole through the shield structure, resulting in openings spaced apart in the first direction, since the digit lines are spaced apart in the first direction.
Regarding dependent claim 15, T1, as modified by L1, further discloses in L1 FIG. 4 and associated text The semiconductor device according to claim 11, further comprising: an insulating interlayer in the openings extending through the bit line shield plate (second insulating layer and second spacer insulating layer 173B, together interpreted as a first insulating interlayer, extends through 160); and contact plugs extending through the insulating interlayer to contact surfaces of the bit line structures, respectively (second contact plugs 175B extend through 173B, contacting T1’s DL1-DL4, as combined).
Claims 1-9 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over T1, and further in view of L1 and Maejima et al. (US 20210125660 A1, hereinafter M1).
Regarding independent claim 1, T1 discloses in T1 FIG. 22A-22C, and 23-24 and associated text A semiconductor device comprising: a lower circuit pattern on a substrate (control circuitry of tier 1 (168) in T1 FIG. 24, which may be supported by (read “on”) a substrate (T1 (115))); a bit line shield structure (comprising reference structure 90 and shield lines 66) on the lower circuit pattern (66/90 are in memory array 98, which is tier 2 (170) in T1 FIG. 24, which is on the control circuitry tier 1 (168)), a bit line structure on the bit line shield structure (any of digit lines DL1-DL4 – interpreted as bit lines – on 90), the bit line structure at least partially overlapping the bit line shield structure in a vertical direction substantially perpendicular to an upper surface of the substrate (digit lines DL1-DL4 overlap in the z-direction, as shown in T1 FIG. 22A-22B); a channel on the bit line structure (channel regions 84 on DL1-DL4); and a capacitor on the channel (storage element 94 is a capacitor as shown in T1 FIG. 23 and stated in T1 (111)), wherein the capacitor is electrically connected to the channel (94 is connected to 84 through source/drain regions 80).
T1 does not explicitly disclose the bit line shield structure including an opening extending therethrough; a first insulating interlayer in the opening extending through the bit line shield structure; a first contact plug extending through the first insulating interlayer to contact the bit line structure, or the first contact plug being electrically connected to the lower circuit pattern.
However, in the same field of endeavor, L1 discloses in L1 FIG. 4 and associated text the bit line shield structure including an opening extending therethrough (shielding pattern 160 has gaps corresponding to 175B); a first insulating interlayer in the opening extending through the bit line shield structure (second insulating layer and second spacer insulating layer 173B, together interpreted as a first insulating interlayer, extends through 160); a first contact plug extending through the first insulating interlayer (second contact plugs 175B extend through 173B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the contact plug and corresponding structures of L1 with the device of T1 to provide a first contact plug to contact the bit line structure through the T1’s shield 66/90 to connect the bit line to underlying structures with reduced resistance and coupling noise (L1 [0093]).
Additionally, in the same field of endeavor, M1 discloses in M1 FIG. 5 and 15 and associated text the first contact plug being electrically connected to the lower circuit pattern (contact V1 – corresponding to the first contact plug since it contacts a bit line BL/34 – is electrically connected to circuitry in the lower portion of CMOS chip CC in the sense amplifier region SR, including transistor T8, as shown in M1 FIG. 15, which is a part of a sense amplifier SA circuit, as shown in M1 FIG. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the connection between a bit line contact plug and lower circuit pattern and corresponding details (i.e. the structure of CMOS chip CC and the connection between it and the bit line, since the control circuitry 168/tier 1 of T1 is not provide in detail) of M1 with the device of T1, as modified by L1, to provide read capabilities for the bit line through connection to a sense amplifier in the lower wiring (M1 [0077]).
Regarding dependent claim 2, T1, as modified by L1 and M1, further discloses in T1 FIG. 22A-22B and associated text The semiconductor device according to claim 1, further comprising a plurality of bit line structures, wherein the bit line structure is included among the plurality of bit line structures (digit lines DL1-DL4), wherein the plurality of bit line structures are spaced apart along a first direction that is substantially parallel to the upper surface of the substrate (DL1-DL4 are spaced apart in the x direction), and each of the plurality of bit line structures extends on the bit line shield structure in a second direction that is substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction (DL1-DL4 extend in the y-direction, which is perpendicular to the x-direction; note that while only DL2 is shown extending in the y-direction in T1 FIG. 22B, each of DL1-DL4 similarly do so (T1 (40))).
Regarding dependent claim 3, T1, as modified by L1 and M1, further discloses in L1 FIG. 5B and associated text The semiconductor device according to claim 2, further comprising a plurality of openings in the bit line shield structure, wherein the opening is included among the plurality of openings (a plurality of openings corresponding to plugs 175B are shown), wherein the plurality of openings are spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate, the third direction defining an acute angle with respect to the first and second directions (please refer to the annotated L1 FIG. 5B below).
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Regarding dependent claim 4, T1, as modified by L1 and M1, further discloses in L1 FIG. 5B and associated text The semiconductor device according to claim 2, wherein the opening extends in a third direction substantially parallel to the upper surface of the substrate, the third direction defining an acute angle with respect to the first and second directions (please refer to the annotated L1 FIG. 5B above).
Regarding dependent claim 5, T1, as modified by L1 and M1, further discloses in L1 FIG. 5A-5B and associated text The semiconductor device according to claim 2, further comprising a plurality of openings in the bit line shield structure and spaced apart from each other in the first direction (openings corresponding to plugs 175B and 175A are spaced apart in a direction – corresponding to the first direction in that it is the direction in which bit lines 143B are spaced apart in L1 FIG. 5A), wherein the opening is included among the plurality of openings, wherein each of the plurality of openings extends in the second direction (the openings extend in a direction perpendicular to the first direction as interpreted, corresponding to the second direction; see also the annotated L1 FIG. 5B above, where the second direction as interpreted is labeled as D2).
Additionally, if not explicitly disclosed by L1, which the examiner does not concede, the references as combined would have this claimed structure, since one of ordinary skill in the art before the effective filing date of the invention would be motivated to combine the references such that each of the bit/digit lines DL1-DL4 of T1 could be read by connections through the holes of L1 to lower circuit patterns of M1, providing each digit line with a corresponding hole through the shield structure, resulting in holes spaced apart in the first direction, since the digit lines are spaced apart in the first direction.
Regarding dependent claim 6, T1, as modified by L1 and M1, further discloses in T1 FIG. 22A and 22C and associated text The semiconductor device according to claim 1, wherein the bit line shield structure comprises: a bit line shield plate having a planar surface extending in first and second directions that are substantially parallel to the upper surface of the substrate (reference structure 90, considered a bit line shield plate, extends in the x- and y-directions, as shown in T1 FIG. 22A and 22B, respectively); and bit line shield fins on the bit line shield plate, each of the bit line shield fins protruding in the vertical direction and extending in the second direction, wherein the bit line shield fins are spaced apart from each other in the first direction (conductive shield material 44 of the shield 66/90 protrude in the z-direction, extend in the y-direction, and are spaced apart in the x-direction, as shown).
Regarding dependent claim 7, T1, as modified by L1 and M1, further discloses the semiconductor device according to claim 6, wherein the bit line structure is on the bit line shield plate between immediately adjacent ones of the bit line shield fins (DL1-DL4 are on 90 and between fins 44).
Regarding dependent claim 8, T1, as modified by L1 and M1, further discloses in M1 FIG. 15 and L1 FIG. 4 and associated text The semiconductor device according to claim 1, further comprising: a second insulating interlayer on the substrate between the first insulating interlayer and the lower circuit pattern (the material (indicated in the annotated M1 FIG. 15 below) over the lower circuit pattern (transistor T8, inter alia) is interpreted as a second insulating interlayer); a first bonding layer on the second insulating interlayer (layers of CMOS chip CC at/near the interface between MC and CC (indicated in the annotated M1 FIG. 15 below) are interpreted as a first bonding layer); and a second bonding layer on the first bonding layer (layers of memory chip MC at/near the interface between MC and CC (indicated in the annotated M1 FIG. 15 below) are interpreted as a second bonding layer), wherein the first insulating interlayer is on the second bonding layer (as combined, L1’s 171 and 173B, previously interpreted together as the first insulating insulator layer, is between a layer corresponding to a bit line and another line, which would correspond to material between e.g. metal layers 34 and 35, which are on the second bonding layer (see also annotated M1 FIG. 15 below, which depicts structures of the combined references in the context of the connection between the bit line and lower circuit pattern in addition to those features disclosed by M1 alone)), and extends on a surface of the bit line shield structure facing the second bonding layer (in L1 FIG. 4, 171 extends on a surface of shield 160 which faces away from the memory stack structure, corresponding to a surface facing the second bonding layer in M1 FIG. 15 (see also annotated M1 FIG. 15 below)), and wherein the first contact plug partially extends through the second bonding layer (V2, corresponding to a portion of the first contact plug, partially extends into the second bonding layer, as shown in annotated M1 FIG. 15 below).
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Regarding dependent claim 9, T1, as modified by L1 and M1, further discloses in M1 FIG. 15 and associated text The semiconductor device according to claim 8, further comprising: a first conductive bonding pad in the second bonding layer (conductor layer 36/bonding pad BP), the first conductive bonding pad contacting a surface of the first contact plug (36/BP contacts V2, corresponding to a part of the first contact plug); a second contact plug in the first bonding layer (columnar contacts C1-C3), the second contact plug contacting the lower circuit pattern (C1 contacts conductor layer 51, corresponding to the lower circuit pattern); and a second conductive bonding pad in the first bonding layer (conductor layer 54/bonding pad BP), the second conductive bonding pad contacting a surface of the second contact plug and a surface of the first conductive bonding pad (54/BP contacts C3 and 36/BP).
Regarding dependent claim 16, T1, as modified by L1, discloses in T1 FIG. 24 and associated text The semiconductor device according to claim 15, further comprising: lower circuit patterns on the substrate (control circuitry tier 1/168 is supported by (read “on”) a substrate (T1 (115))). They do not explicitly disclose the contact plugs are electrically connected to the lower circuit patterns.
However, in the same field of endeavor, M1 discloses in M1 FIG. 15 and associated text the contact plugs are electrically connected to the lower circuit patterns (contact V1 – corresponding to the first contact plug since it contacts a bit line BL/34 – is electrically connected to circuitry in the lower portion of CMOS chip CC in the sense amplifier region SR, including transistor T8, as shown in M1 FIG. 15, which is a part of a sense amplifier SA circuit, as shown in M1 FIG. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the connection between a bit line contact plug and lower circuit pattern and corresponding details (i.e. the structure of CMOS chip CC and the connection between it and the bit line, since the control circuitry 168/tier 1 of T1 is not provide in detail) of M1 with the device of T1, as modified by L1, to provide read capabilities for the bit line through connection to a sense amplifier in the lower wiring (M1 [0077]).
Regarding independent claim 17, T1 discloses in T1 FIG. 22A-22C and 23-24 and associated text A semiconductor device comprising: a lower circuit pattern on a substrate (control circuitry of tier 1 (168) in T1 FIG. 24, which may be supported by (read “on”) a substrate (T1 (115))); a bit line shield structure (comprising reference structure 90 and shield lines 66); a bit line structure on the bit line shield structure (any of digit lines DL1-DL4 – interpreted as bit lines – on 90), the bit line structure at least partially overlapping the bit line shield structure in the vertical direction (digit lines DL1-DL4 overlap in the z-direction, as shown in T1 FIG. 22A-22B); a channel on the bit line structure (channel regions 84 on DL1-DL4); and a capacitor on the channel (storage element 94 is a capacitor as shown in T1 FIG. 23 and stated in T1 (111)), the capacitor being electrically connected to the channel (94 is connected to 84 through source/drain regions 80).
T1 does not explicitly disclose first and second bonding layers stacked on the lower circuit pattern in a vertical direction substantially perpendicular to an upper surface of the substrate; the bit line shield structure being on the second bonding layer, the bit line shield structure including an opening extending therethrough, an insulating interlayer, wherein the insulating interlayer is on a surface of the bit line shield structure and comprises a portion in the opening; the insulating interlayer being between the second bonding layer and the bit line shield structure, a contact plug extending through the portion of the insulating interlayer in the opening to contact the bit line structure, or the contact plug being electrically connected to the lower circuit pattern.
However, in the same field of endeavor, L1 discloses in L1 FIG. 4 and associated text the bit line shield structure including an opening extending therethrough (shielding pattern 160 has gaps corresponding to 175B), an insulating interlayer, wherein the insulating interlayer is on a surface of the bit line shield structure and comprises a portion in the opening (second insulating layer and second spacer insulating layer 173B, together interpreted as an insulating interlayer, is on 160 and includes 173B in a corresponding opening in 160); and a contact plug extending through the portion of the insulating interlayer in the opening (second contact plugs 175B extend through 173B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the contact plug and corresponding structures of L1 with the device of T1 to provide a first contact plug to contact the bit line structure through the T1’s shield 66/90 to connect the bit line to underlying structures with reduced resistance and coupling noise (L1 [0093]).
Additionally, in the same field of endeavor, M1 discloses in M1 FIG. 15 and associated text first and second bonding layers stacked on the lower circuit pattern in a vertical direction substantially perpendicular to an upper surface of the substrate (portions of CMOS chip CC and memory chip MC at/near the interface of MC and CC, which are stacked in the z-direction, perpendicular to semiconductor substrate 50, as shown in annotated M1 FIG. 15 below); and the contact plug being electrically connected to the lower circuit pattern (contact V1 – corresponding to the first contact plug since it contacts a bit line BL/34 – is electrically connected to circuitry in the lower portion of CMOS chip CC in the sense amplifier region SR, including transistor T8, as shown in M1 FIG. 15, which is a part of a sense amplifier SA circuit, as shown in M1 FIG. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the connection between a bit line contact plug and lower circuit pattern and corresponding details (i.e. the structure of CMOS chip CC and the connection between it and the bit line, since the control circuitry 168/tier 1 of T1 is not provided in detail) of M1 with the device of T1, as modified by L1, to provide read capabilities for the bit line through connection to a sense amplifier in the lower wiring (M1 [0077]). The resulting structure would be such that the bit line shield structure is on the second bonding layer (T1’s 66/90 are adjacent to DL1-DL4 in the memory chip 98, corresponding to a position on the second bonding layer of M1, as interpreted and shown in annotated M1 FIG. 15 below) and the insulating interlayer is between the second bonding layer and the bit line shield structure (as combined, L1’s 171 and 173B, previously interpreted together as the first insulating insulator layer, is between a layer corresponding to a bit line and another line, which would correspond to material between e.g. metal layers 34 and 35, which are on the second bonding layer (see also annotated M1 FIG. 15 below, which depicts structures of the combined references in the context of the connection between the bit line and lower circuit pattern in addition to those features disclosed by M1 alone)).
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Regarding dependent claim 18, T1, as modified by L1 and M1, further discloses in T1 FIG. 22A-22B and associated text The semiconductor device according to claim 17, further comprising a plurality of bit line structures, wherein the bit line structure is included among the plurality of bit line structures (digit lines DL1-DL4), wherein the plurality of bit line structures are spaced apart along a first direction that is substantially parallel to the upper surface of the substrate (DL1-DL4 are spaced apart in the x direction), and each of the plurality of bit line structures extends on the bit line shield structure in a second direction that is substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction (DL1-DL4 extend in the y-direction, which is perpendicular to the x-direction; note that while only DL2 is shown extending in the y-direction in T1 FIG. 22B, each of DL1-DL4 similarly do so (T1 (40))).
Regarding dependent claim 19, T1, as modified by L1 and M1, further discloses in L1 FIG. 5B and associated text The semiconductor device according to claim 18, further comprising a plurality of openings in the bit line shield structure, wherein the opening is included among the plurality of openings (a plurality of openings corresponding to plugs 175B are shown), wherein the plurality of openings are spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate, the third direction defining an acute angle with respect to the first and second directions (please refer to the annotated L1 FIG. 5B below).
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Regarding dependent claim 20, T1, as modified by L1 and M1, further discloses in T1 FIG. 22A and 22C and associated text The semiconductor device according to claim 18, wherein the bit line shield structure comprises: a bit line shield plate having a planar surface extending in the first and second directions that are substantially parallel to the upper surface of the substrate (reference structure 90, considered a bit line shield plate, extends in the x- and y-directions, as shown in T1 FIG. 22A and 22B, respectively); and bit line shield fins on the bit line shield plate, each of the bit line shield fins protruding in the vertical direction, wherein the bit line shield fins are spaced apart from each other in the first direction (conductive shield material 44 of the shield 66/90 protrude in the z-direction and are spaced apart in the x-direction, as shown).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over T1, and further in view of L1, M1, and Ashidate et al. (US 20230395499 A1, hereinafter A1).
Regarding dependent claim 10, T1, as modified by L1 and M1, discloses in M1 FIG. 15 and associated text The semiconductor device according to claim 9, wherein each of the first and second conductive bonding pads comprises copper (36 and 54 contain copper (M1 [0137] and [0160], respectively)). They do not explicitly disclose each of the first and second bonding layers comprises silicon carbonitride.
However, in the same field of endeavor, A1 discloses in A1 FIG. 9 and associated text each of the first and second bonding layers comprises silicon carbonitride (insulators 74 at bonding face S1, corresponding to the first and second bonding layers at the interface of M1’s MC and CC, are silicon carbonitride (A1 [0073])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the silicon carbonitride films of A1 with the device of T1, as modified by L1 and M1, to prevent diffusion of Cu atoms from bonding pads (A1 [0073]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20090004843 A1, pertaining to a shielded bit line structure with through-vias similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights