Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 1, 3-6, and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng (US 20250015021 A1, effectively filed 3/20/2022) in view of Chen (US 20230361016 A1).
Regarding claim 1, Zeng discloses a power chip embedded encapsulation module (Fig. 5G. Note: 1) “power chip embedded” is interpreted here consistent with Applicant’s disclosure, See Fig. 16 which shows chips 21 generally “embedded” within a resultant device; 2) “encapsulation module” is interpreted here consistent with the special meaning given by Applicant, which is a module generally enclosing chips 21, and therefore encapsulating these chips. The examiner finds these meanings acceptable, though different from the ordinary and customary meaning of “encapsulation”, which generally means a polymer molding material.) comprising:
a chip substrate (2) comprising a first circuit substrate (See annotated figure) and an electrically conductive sheet (See annotated figure; [0299]: “circuit” teaches at least some amount of electrical conductivity) embedded in said first circuit substrate;
a ceramic substrate (3/4/5, See annotated figure; [0285]: “a ceramic insulating plate”), provided on (indirectly on) a first surface side (201) of said chip substrate;
a second circuit substrate, provided on a second surface side of said chip substrate;
a plurality of power chips (Q1, Q2; [0003]: “semiconductor power devices”) encapsulated between (sandwiched “between”) said chip substrate and said ceramic substrate;
wherein a first side of each of said power chips (See annotated figure for side designation) is electrically connected (See Fig. 5F showing electrical schematic and annotated electrical path, thus “electrically connected”) to said first circuit substrate and said electrically conductive sheet, and
a second side of each of said power chips (See annotated figure for side designation) relative to said first side is electrically connected (See Fig. 5F showing electrical schematic and annotated electrical path, thus “electrically connected”) to said ceramic substrate;
a plurality of thermally conductive ceramic blocks, each of which is connected to said electrically conductive sheet and said ceramic substrate on opposite sides, respectively; wherein said thermally conductive ceramic blocks and said power chips are alternately disposed along a length direction of said electrically conductive sheet.
Illustrated below is a marked and annotated figure of Fig. 5G of Zeng.
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Zeng fails to teach the “power chip embedded encapsulation module” embodiment of Fig. 5G including “a second circuit substrate, provided on a second surface side of said chip substrate”. Nevertheless, Zeng discloses a plurality of alternative embodiments (at least the embodiments of Figs. 23 and 24A) including the chip substrate, ceramic substrate, and power chips; and this plurality of alternative embodiments teaches a second circuit substrate (22), provided on a second surface side of said chip substrate (See annotated figure for surface designation). Modifying the module embodiment of Fig. 5G by including a second circuit substrate in the same way would arrive at the claimed substrate configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Zeng teaches the second circuit substrate is a structure included with modules to enable operation of the module ([0373]: “connected with the client main board”). Zeng provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the second substrate in that it would enable including additional circuitry for operation of the module ([0373]: “provided with a high-frequency decoupling capacitor 23, a high-voltage isolation driver or a controller and other system control elements”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed substrate configuration because it would enable including additional circuitry for operation of the module. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 23 of Zeng.
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Zeng fails to teach “a plurality of thermally conductive ceramic blocks, each of which is connected to said electrically conductive sheet and said ceramic substrate on opposite sides, respectively; wherein said thermally conductive ceramic blocks and said power chips are alternately disposed along a length direction of said electrically conductive sheet”.
Chen discloses a plurality of thermally conductive ceramic blocks (Fig. 5: 310a/310b/310c. Note: [0061]: “ceramic” teaches “ceramic” material compositions for the blocks, and this material necessarily has at least some amount of thermal conductivity. Thus, the blocks are “thermally conductive” within the breadth of the claim.), each of which is connected (at least indirectly “connected”) to said electrically conductive sheet (Fig. 4D: 230a, See annotated figure) and said ceramic substrate (Fig. 4D: generic substrate 240 is relied upon here) on opposite sides, respectively; wherein said thermally conductive ceramic blocks and said power chips (315) are alternately disposed along a length direction (See annotated figure for direction designation) of said electrically conductive sheet
Modifying the chip configuration of Zeng by including blocks in the same way as Chen (i.e., between chips) would arrive at the claimed chip and block arrangement. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation: 1) heat dissipation is a design concern (Zeng: [0304]: “solve the heat dissipation problem”; Chen: [0067]: “may be further configured as a heatsink that receives heat 445 from the IC die”); and 2) a gap exists between the chips (Zeng: Fig. 5G: See annotated figure; Chen: Fig. 5: “See annotated figure”). Chen provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the claimed chip and block configuration in that it would protect the module during assembly ([0047]: “to improve a robustness, a quality, and/or a reliability of the semiconductor package”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chip and block configuration because it would protect the module during assembly, thereby enhancing manufacturing yield. MPEP 2143 (I)(G).
Illustrated below are marked and annotated figures of Figs. 5 and 4D of Chen.
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Regarding claim 3, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 1 (Zeng: Fig. 5G), wherein a side of said electrically conductive sheet is provided with a lateral projection (See annotated figure) embedded inside said first circuit substrate.
Regarding claim 4, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 1 (Zeng: Fig. 23), wherein said electrically conductive sheet is provided with pins (Pin A/B/C) projecting to the outside of said encapsulation module.
Regarding claim 5, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 1 (Zeng: Fig. 5G), wherein said ceramic substrate comprises a ceramic core plate (3; [0285]: “a ceramic insulating plate”) and a metal conductive layer (5; [0285]: “metal layer”) and a metal heat dissipation layer (4; [0285]: “metal layer”. Note: this material necessarily has at least some amount of thermal conductivity. Thus, the layer is a “heat dissipation layer” within the breadth of the claim.) disposed on opposite sides of said ceramic core plate, respectively, and wherein said metal conductive layer is connected to said power chips (at least indirectly “connected”) and said thermally conductive ceramic blocks (at least indirectly “connected”).
Regarding claim 6, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 5 (Zeng: Fig. 5G), wherein said metal heat dissipation layer is connected to a heat sink (the assembly of all fins 135), said heat sink being provided with heat dissipation fins (fins 135).
Regarding claim 8, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 1 (Zeng: Fig. 23), wherein said second circuit substrate comprises multi-layer conductive circuits ([0373]: “One side…is connected…The other side…is connected”), conductive circuits of said first circuit substrate being electrically connected to the conductive circuits of said second circuit substrate (through Pins A/B/C).
Regarding claim 9, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 1 (Zeng: Fig. 23), wherein said second circuit substrate is provided with a drive assembly ([0373]: “a high-voltage isolation driver”) and circuit elements ([0373]: “a controller and other system control elements”).
Regarding claim 10, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 1 (Zeng: Fig. 5G), wherein said first circuit substrate is provided with at least one set of said electrically conductive sheets (the grouping of all sheets is being designated here as “one set”), each set of said electrically conductive sheets comprising a first electrically conductive sheet (See annotated figure) and a second electrically conductive sheet (See annotated figure), said first electrically conductive sheet and said second electrically conductive sheet being provided with said thermally conductive ceramic blocks (at least indirectly) and said power chips (at least indirectly) alternately (“alternately” is addressed in the claim 1 rejection by relating the gaps of Zeng and Chen).
Regarding claim 11, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 1 (Zeng: Fig. 5G), wherein each of said power chips is provided with a source (Source) and a gate (Gate) on a first side of the power chip (See annotated figure for “side” designation. These structures are either directly “on” or indirectly “on”), and each of said power chips is provided with a drain (Drain. Note: Q2 inadvertently is illustrated with Source twice, but Drain is missing. This is a defect of the illustration based on [0301]: “drain electrode”.) on a second side of the power chip (See annotated figure for “side” designation. This structure is either directly “on” or indirectly “on”), and said source and said gate are electrically connected (at least indirectly “connected”) to said electrically conductive sheet, and said first circuit substrate, respectively, and said drain is electrically connected (at least indirectly “connected”) to said ceramic substrate.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zeng in view of Chen as applied to claim 6 above, and further in view of Rippel (US 9443786 B1).
Regarding claim 7, Zeng in view of Chen discloses the power chip embedded encapsulation module according to claim 6 (Zeng: Fig. 5G), wherein said heat sink forms a cavity sealingly connected (directly “connected”) to said ceramic substrate to accommodate a cooling medium (Cooling liquid), said cavity having an inner wall provided with a capillary structure.
Zeng fails to teach the “heat sink forms a cavity”. Thus, Zeng in view of Chen fails to teach “wherein said heat sink forms a cavity sealingly connected to said ceramic substrate to accommodate a cooling medium, said cavity having an inner wall provided with a capillary structure”.
Rippel discloses wherein said heat sink (Fig. 3: 122) forms a cavity (col. 5, lines. 7-24: “through the fins…serpentine”) sealingly connected (col. 4, line56-col. 5, line 6: “bonded”) to said ceramic substrate (generic substrate 121 is relied upon here) to accommodate a cooling medium (col. 5, lines. 7-24: “coolant”), said cavity having an inner wall (See annotated figure) provided with a capillary structure (the figure shows the fin is a hollow tube, thus it is “a capillary structure”).
Modifying the heat sink (of Zeng in view of Chen), by incorporating the cavity configuration (of Rippel) would arrive at the claimed heat sink and substrate configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the heat sink incorporates a cooling medium (Zeng: Fig. 5G: Cooling liquid; Rippel: col. 5, lines. 7-24: “coolant”). Rippel provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the cavity configuration in that it would improve heat dissipation of the module (col. 3, lines 35-38: “increase the flow and effectiveness of a coolant”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed cavity and substrate configuration because it would improve heat dissipation of the module. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 3 of Rippel.
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Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 2 is the inclusion of the limitation “wherein the size of the thermally conductive ceramic blocks located in the middle is twice the size of the thermally conductive ceramic blocks located at both ends along the length direction of said electrically conductive sheet” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “size”, “twice”, “middle”, and “both ends” in combination with all other limitations in claims 2 and 1. The particular configuration claimed goes beyond the teachings or obvious suggestions of the prior art of record, and the analogous structures found elsewhere in the prior art. More specifically, variations in block size were found elsewhere in the prior art, but varying them by the amounts claimed at the arrangements claimed was not found or rendered obvious. MPEP 2144.04 (IV)(A) and (B); MPEP 2144.04 (VI)(C).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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