DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 04/08/0226 Amendment.
Claims 1-20 are pending. Claims 15-20 have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,250,894 to PGPub. 2009/0296514 to Yeh (hereafter Yeh) in view of Kwon et al. (hereafter Kwon) in view of US 9,030,895 to Miura et al. (hereafter Miura).
Regarding independent claim 1, Yeh teaches an operation method of a
receiving a mode register set (MRS) command through row command/address signal lines in an idle mode (FIGS. 2-3: receiving MRS command through row pins PIN_R0 - PIN_R5 corresponding to RowAdr0 - RowAdr5, see paragraphs [0018]-[0019]. It is well known that in modern memory technology, the initialization sequence before any data access is Reset -> CKE high -> Precharge All -> MRS (MR6, MR5, ... MR0) -> ZQ Calibration -> ACT, there appears the memory device should be in idle mode when MRS command is sent to memory device prior to ACT command), wherein in the idle mode, a first command/address (CA) buffer is in an inactive state (FIGD. 2 and 4: first/column CA buffer receiving signals through column pins PIN_C0 – PIN_C4 corresponding to ColAdr0-ColAdr4. There appears the first/column CA buffer should be inactive during early stage of initialization sequence because ACT command has not yet received and therefore column address is not yet needed) and a second CA buffer is in an active state (FIG. 3: there appears the second/row CA buffer receiving signals on RowAdr0-RowAdr5 should be active during early stage of initialization sequence because MRS command is sent through it);
inherently performing an MRS operation in response to the MRS command;
receiving an activate (ACT) command through the row command/address signal lines in the idle mode (FIG. 3: receiving ACT command through row command signal lines on row pins R_P0 to R_P9 of FIG. 12A); and
inherently switching to an activate mode in response to the ACT command (because ACT command is to activate the memory for data access),
Yeh does not explicit teach the strikethrough limitations.
Kwon teaches an operation method of a high bandwidth memory (HBM) device (see FIG. 15).
Miura teaches a memory chip receives MRS and ACT commands when it is in idle mode.
Since Yeh, Kwon and Miura are all from the same field of endeavor, the purpose disclosed by Yeh and Miura would have been recognized in the pertinent art of Kwon.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
send MRS and ACT commands through row column/address signal lines as suggested in Yeh to the HBM device of Kwon because it possible in memory technology;
realize that when the memory device of Kwon is placed in active mode after MRS and ACT commands have been received and decoded through second/row CA buffer, the remain first/column CA buffer should also be placed in active state, in order to get ready for receiving column address for data access responsive to ACT command;
realize that Miura is provided to support Examiner’s statement that the memory device is placed in idle mode during initialization sequence, which comprising sending MRS then ACT commands to the memory device.
Regarding dependent claim 2, Yeh teaches the column CA buffer as first CA buffer. Kwon teaches a memory device includes a column command/address (CA) buffer configured to buffer column command/address signals, and wherein, in the idle mode, the column CA buffer is in an inactive state such that current does not flow in the column CA buffer (FIG. 12B: because in no operation column command mode CNOP, column pins C_P0 to C_P7 are set to valid value V of high level H or low level L, which should result in no current flowing).
Regarding dependent claim 3, Yeh teaches the column CA buffer as first CA buffer. Kwon teaches changing a state of the column CA buffer to an active state in which current flows therein, in response to the ACT command (because in response to ACT command, RD/WR command is inputted, column pins C_P0 to C_P7 are set to value of signal lines).
Regarding dependent claim 4, Miura teaches wherein the MRS operation comprises: decoding the MRS command; and performing the MRS operation based on a decoding result of the decoding of the MRS command (see FIGS. 6, 9 and 22:63-67).
Regarding dependent claim 5, Miura teaches receiving a precharge command in the activate mode; and performing a precharge operation in response to the precharge command and switching to the idle mode (FIG. 9: memory device is transitioning from IDLE [Wingdings font/0xE0] ACTIVE [Wingdings font/0xE0] PRECHARGE [Wingdings font/0xE0] IDLE, see 23:34-62).
Regarding dependent claim 6, Yeh teaches wherein the memory device further comprises a row CA buffer as second CA buffer. The row CA buffer is configured to buffer row command/address signals, and should be in the active state in idle and active modes because the row CA buffer receiving MRS and ACT commands.
Regarding dependent claim 7, Miura teaches performing, by the memory device, a read operation of data in the activate mode (FIG. 6: read operation of data is in active mode).
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of US 9,202,551 to Bains et al. (hereafter Bains) in view of US 9,030,895 to Miura et al. (hereafter Miura).
Regarding independent claim 8, Yeh teaches an operation method of a
FIGS. 2 and 5: e.g. first mode corresponding to transmitting row address command packets using row pins and column address command packets using column pins), wherein a column command/address (CA) buffer configured to buffer a column command/address signal is in an inactive state in the first mode FIGS. 2-3: receiving MRS command through row pins PIN_R0 - PIN_R5 corresponding to RowAdr0 - RowAdr5, see paragraphs [0018]-[0019]. It is well known that in modern memory technology, the initialization sequence before any data access is Reset -> CKE high -> Precharge All -> MRS (MR6, MR5, ... MR0) -> ZQ Calibration -> ACT, there appears the memory device should be in idle mode when MRS and ACT commands are sent to memory device);
inherently performing a mode register set (MRS) operation in the idle mode; and
in the idle mode, receiving an activate (ACT) command through a row command/address signal line (FIG. 3: receiving ACT command through row command signal lines on row pins R_P0 to R_P9 of FIG. 12A) and switching to activate mode (because ACT command is to activate the memory for data access),
Yeh does not explicit teach the strikethrough limitations.
Bains teaches an operation method of an high bandwidth memory (HBM) device, the method comprising selecting one of a first mode (FIG. 8: handle column and row commands separately in step 820) and a second mode (FIG. 8: handle column and row commands on shared bus in step 825) in an idle mode (FIG. 8: i.e. during memory initialization in step 805), wherein a column command/address (CA) buffer configured to buffer a column command/address signal is FIG. 6: because both MRS and ACT commands are received and decoded by row column CA pin when the HBM device is in second mode).
Miura teaches a memory chip receives MRS and ACT commands when it is in idle mode.
Since Yeh, Bains and Miura are all from the same field of endeavor, the purpose disclosed by Bains and Miura would have been recognized in the pertinent art of Yeh.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
apply the teaching of Bains to memory device of Yeh in order to reducing number of connections as needed (see Bains, 1:34-42);
realize that when the memory device of Bains is placed in active mode after MRS and ACT commands have been received and decoded through second/row CA buffer, the remain first/column CA buffer should also be placed in active state, in order to get ready for receiving column address for data access responsive to ACT command;
realize that Miura is provided to support Examiner’s statement that the memory device is placed in idle mode during initialization sequence, which comprising sending MRS then ACT commands to the memory device.
Regarding dependent claim 9, Bains teaches the MRS command is received through row command/address signal lines (FIG. 6: when MRS command is decoded via signals on row column pins RC0-RC7 when the HBM device is in second mode).
Regarding dependent claim 10, Bains teaches wherein the performing of the MRS operation in the idle mode includes: receiving an MRS command through a column command/address signal line (see FIG. 12B); and inherently performing the MRS operation in response to the MRS command.
Regarding dependent claim 11, Bains teaches receiving, from a memory controller that is configured to control the HBM device, a control signal; and switching between the first mode and the second mode in response to the control signal received from the memory controller (FIG. 8: control signal from command bus in step 812).
Regarding dependent claim 12, Bains teaches changing a state of the inherent column CA buffer to an active state in response to the ACT command (FIG. 6: because ACT command is decoded via signals on row column pins RC0-RC7 when the HBM device is in second mode).
Regarding dependent claim 13, Miura teaches receiving a precharge command in the activate mode; and performing a precharge operation on the memory device in response to the precharge command and switching to the idle mode (FIG. 9: memory device is transitioning from IDLE [Wingdings font/0xE0] ACTIVE [Wingdings font/0xE0] PRECHARGE [Wingdings font/0xE0] IDLE, see 23:34-62).
Regarding dependent claim 14, Bains teaches wherein the memory device includes an inherent row CA buffer configured to buffer a row command/address signal, and wherein, in the idle mode and the activate mode, the row CA buffer is in the active state (FIG. 6: inherent buffer couples to row column pins RC0-RC7, which should be active for transmitting any row or column command/address).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 8 have been considered but are moot because the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
May 14, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
Prosecution Insights