DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed
in Taiwan, TW 112130384 on September 11, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/22/2024 and 07/19/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20210225741 A1).
Regarding Claim 1, Chen et al. teaches a lead frame, adapted to be applied to a quad flat no-lead (QFN) package structure, wherein the lead frame comprises:
a die-bonding region 10 configured to allow a die to be disposed (Fig. 6: 10, paragraph 0023);
and a plurality of leads 20 disposed on a periphery of the die-bonding region 10 (Fig. 6: 20, 10, paragraph 0023),
wherein the leads 20 comprise:
at least one first lead 20a disposed on one side of the die-bonding region 10 (Fig. 6: 20a, 10, paragraph 0024),
wherein the at least one first lead 20a comprises a first edge pin 22a, an internal pin 25, and a first extension part 21a (Fig. 7: 20a, 22a, 25, 21a, paragraph 0024, 0025),
the internal pin 25 is connected to a bottom surface of one of two ends of the first extension part 21a (Fig. 7: 25, 21a, paragraph 0025),
the first edge pin 22a is connected to a bottom surface of the other end of the first extension part 21a (Fig. 7: 25, 21a, 22a, paragraph 0025),
and the internal pin 25 is nearer to the die-bonding region 10 with respect to the first edge pin 22a (Fig. 7: 25, 10, 22a);
and a plurality of second leads 22b (Fig. 6: 20b, paragraph 0024),
wherein each of the second leads 20b comprises a second edge pin 22b and a second extension part 21b, the second edge pin 22b is connected to a bottom surface of one of two ends of the second extension part 21b, and the other end of the second extension part 21b is nearer to the die-bonding region 10 with respect to the end of the second extension part 21b to which the second edge pin 22b is connected (Fig. 9: 20b, 21b, 22b, 10, paragraph 0026).
Regarding Claim 2, Chen et al. teaches the lead frame according to claim 1, wherein an upper surface of the end of the first extension part 21a which is connected to the internal pin 25 is configured to be connected to the die 50 through wire-bonding (see Fig. 13: 25, 21a, 50, paragraph 0038).
Regarding Claim 6, Chen et al. teaches a semiconductor device, comprising:
a die 50 (Fig. 13: 50, paragraph 0038);
a lead frame 1 adapted to be applied to a QFN package structure (Fig. 13: 1, paragraph 0038, ),
wherein the lead frame 1 comprises:
a die-bonding region 10 configured to allow a die to be disposed (Fig. 6: 10, paragraph 0002, 0023);
and a plurality of leads 20 disposed on a periphery of the die-bonding region 10 (Fig. 6: 20, 10, paragraph 0023),
wherein the leads comprise:
at least one first lead 20a disposed on one side of the die-bonding region 10 (Fig. 6: 20a, 10, paragraph 0024),
wherein the at least one first lead 20a comprises a first edge pin 22a, an internal pin 25, and a first extension part 21a (Fig. 7: 20a, 22a, 25, 21a, paragraph 0024, 0025),
the internal pin 25 is connected to a bottom surface of one of two ends of the first extension part 21a (Fig. 7: 25, 21a, paragraph 0025),
the first edge pin 22a is connected to a bottom surface of the other end of the first extension part 21a (Fig. 7: 25, 21a, 22a, paragraph 0025),
and the internal pin 25 is nearer to the die-bonding region 10 with respect to the first edge pin 22a (Fig. 7: 25, 10, 22a);
and a plurality of second leads 22b (Fig. 6: 20b, paragraph 0024),
wherein each of the second leads 20b comprises a second edge pin 22b and a second extension part 21b, the second edge pin 22b is connected to a bottom surface of one of two ends of the second extension part 21b, and the other end of the second extension part 21b is nearer to the die-bonding region 10 with respect to the end of the second extension part 21b to which the second edge pin 22b is connected (Fig. 9: 20b, 21b, 22b, 10, paragraph 0026);
and a package 3 configured to enclose the die 50 and a portion of the lead frame 1 (Fig. 12: 3, Fig. 13: 1, 50, paragraph 0038).
Regarding Claim 7, Chen et al. teaches the semiconductor device according to claim 6, wherein an upper surface of the end of the first extension part 21a which is connected to the internal pin 25 is configured to be connected to the die 50 through wire-bonding (see Fig. 13: 25, 21a, 50, paragraph 0038).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary reference(s).
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210225741 A1), as applied to Claim 2 above, further in view of Wang et al. (US 20220238419 A1).
Regarding Claim 3, Chen et al. fails to explicitly teach the lead frame according to claim 2, wherein the at least one first lead is configured to transmit a power signal.
However, Wang et al. teaches a lead frame, wherein the at least one first lead is configured to transmit a power signal (paragraph 0051).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Chen et al. and in order to have at least one first lead is configured to transmit a power signal. Doing so would enable power delivery to the die.
Regarding Claim 4, Chen et al. teaches the lead frame according to claim 3, wherein an upper surface of the other end of the second extension part 21b is configured to be connected to the die through wire-bonding (not shown in figures but see paragraph 0026, which states the second extension part 21b has a bonding portion 23b close to the die region 10 configured to be connected using bonding wire).
Regarding Claim 5, Chen et al. teaches the lead frame according to claim 4, wherein the leads 20 further comprise: a ground lead 20’, comprising a ground central pin, a plurality of ground extension parts and a plurality of ground edge pins, wherein one of two ends of each of the ground extension parts is connected to a corresponding one of the ground edge pins, the other end of each of the ground extension parts is connected to the ground central pin, and for each of the ground extension parts, the other end is nearer to the die-bonding region 10 with respect to the end to which the ground edge pin is connected (see annotated Fig. 3: {20’, central pin, extension part, edge pin}, which shows a clear view of the lead 20’ of Fig. 6).
Chen et al. fails to explicitly teach the lead 20’ is a ground lead.
However, Wang et al. teaches a ground lead 29 arranged on the die pad 33 in a similar manner to that of Chen et al. (Fig. 18: 29, 33, paragraph 0055).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Chen et al. and Wang et al. in order to configure the central lead of Chen as a ground lead. Doing so would enable the transmission of ground signals to the outside of the semiconductor device, as recognized by Wang et al. (paragraph 0055).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210225741 A1), as applied to Claim 2 above, further in view of Wang et al. (US 20220238419 A1).
Regarding Claim 8, Chen et al. fails to explicitly teach the semiconductor device according to claim 7, wherein the at least one first lead is configured to transmit a power signal.
However, Wang et al. teaches a semiconductor device, wherein the at least one first lead is configured to transmit a power signal (paragraph 0051).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Chen et al. and Wang et al. in order to have at least one first lead is configured to transmit a power signal. Doing so would enable power delivery to the die.
Regarding Claim 9, Chen et al. teaches the semiconductor device according to claim 8, wherein an upper surface of the other end of the second extension part 21b is configured to be connected to the die through wire-bonding (not shown in figures but see paragraph 0026, which states the second extension part 21b has a bonding portion 23b close to the die region 10 configured to be connected using bonding wire).
Regarding Claim 10, Chen et al. teaches the semiconductor device according to claim 9, wherein the leads 20 further comprise: a ground lead 20’, comprising a ground central pin, a plurality of ground extension parts and a plurality of ground edge pins, wherein one of two ends of each of the ground extension parts is connected to a corresponding one of the ground edge pins, the other end of each of the ground extension parts is connected to the ground central pin, and for each of the ground extension parts, the other end is nearer to the die-bonding region 10 with respect to the end to which the ground edge pin is connected (see annotated Fig. 3: {20’, central pin, extension part, edge pin}, which shows a clear view of the lead 20’ of Fig. 6).
Chen et al. fails to explicitly teach the lead 20’ is a ground lead.
However, Wang et al. teaches a ground lead 29 arranged on the die pad 33 in a similar manner to that of Chen et al. (Fig. 18: 29, 33, paragraph 0055).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Chen et al. and Wang et al. in order to configure the central lead of Chen as a ground lead. Doing so would enable the transmission of ground signals to the outside of the semiconductor device, as recognized by Wang et al. (paragraph 0055).
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Annotated Fig. 3 of Chen et al. (US 20210225741 A1)
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kasahara et al. (US 20040080025 A1) teaches a lead frame, adapted to be applied to a quad flat no-lead (QFN) package structure comprising a plurality of leads, each comprising an edge pin, an internal pin and an extension part connecting the edge pin and the internal pin
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 06/11/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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