DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: “x 1< x2” should be corrected to x1 < x2 Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 9-16, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajiwara et al. (U.S. Publication No. 2022/0231155 A1; hereinafter Kajiwara) in view of Shirota et al. (U.S. Publication No. 2017/0194474 A1; hereinafter Shirota).
With respect to claim 1, Kajiwara discloses a semiconductor device, comprising: a first electrode [51]; a second electrode [52]; a third electrode [53] including silicon (see ¶[0109]), a position of the third electrode in a first direction from the first electrode to the second electrode being between a position of the first electrode in the first direction and a position of the second electrode in the first direction, the third electrode including a first electrode region and a second electrode region (see Figure 1); a semiconductor member including a first semiconductor layer [10] and a second semiconductor layer [20], the first semiconductor layer [10] including Alx1Ga1-x1N (0≤x1<1) (see ¶[0024]), the first semiconductor layer including a first partial region [11], a second partial region [12], a third partial region [13], a fourth partial region [14], and a fifth partial region [15], a second direction from the first partial region to the first electrode crossing the first direction, a direction from the second partial region to the second electrode being along the second direction, a direction from the third partial region to the first electrode region being along the second direction, a position of the fourth partial region in the first direction being between a position of the first partial region in the first direction and a position of the third partial region in the first direction, a position of the fifth partial region in the first direction being between the position of the third partial region in the first direction and a position of the second partial region in the first direction (See ¶[0025]), the second semiconductor layer including Alx2Ga1-x2N (0<x2≤1, x 1<x2) (see ¶[0026]), the second semiconductor layer including a first semiconductor portion [21] and a second semiconductor portion [22], a direction from the fourth partial region to the first semiconductor portion being along the second direction, a direction from the fifth partial region to the second semiconductor portion being along the second direction, the first electrode region being between the first semiconductor portion and the second semiconductor portion in the first direction, a part of the first semiconductor portion being provided between the fourth partial region and the second electrode region in the second direction (See ¶[0026-0027]); and a first insulating member [41] provided between the semiconductor member and the third electrode. Kajiwara fails to disclose the first electrode region and the second electrode region satisfying a first condition or a second condition, in the first condition, the second electrode region including a first element including at least one selected from the group consisting of P and As, and the first electrode region not including the first element, and in the second condition, a second concentration of the first element in the second electrode region being higher than a first concentration of the first element in the first electrode region.
In the same field of endeavor, Shirota teaches the first electrode region [108] and the second electrode region [106] satisfying a first condition or a second condition, in the first condition, the second electrode region including a first element including at least one selected from the group consisting of P and As, and the first electrode region not including the first element, and in the second condition, a second concentration of the first element in the second electrode region being higher than a first concentration of the first element in the first electrode region (see Figure 1(a) and ¶[0066]). Implementing a two region third electrode, as taught by Shirota allows for increased control over the gate functions of the device, thereby allowing for a normally-off transistor with excelling switching properties to be obtained (See ¶[0033]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 9, the combination of Kajiwara and Shirota discloses wherein the third electrode includes a second element including at least one selected from the group consisting of B and Al (see Shirota ¶[0066]).
With respect to claim 10, the combination of Kajiwara and Shirota fails to explicitly disclose wherein a concentration of the second element in the third electrode is not less than 1×1017 cm−3 and not more than 1×1021 cm−3. However it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the optimum concentration of the elements within the third electrode can be discovered by routine experimentation to provide optimal switching capability of the gate electrode.
With respect to claim 11, the combination of Kajiwara and Shirota discloses wherein the second concentration is not less than 10 times and not more than 1000 times the first concentration.
However, it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the optimum concentration of the elements within the third electrode can be discovered by routine experimentation to provide optimal switching capability of the gate electrode.
With respect to claim 12, the combination of Kajiwara and Shirota discloses wherein the second concentration is not less than 1×1016 cm−3 and not more than 1×1021 cm−3.
However, it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the optimum concentration of the elements within the third electrode can be discovered by routine experimentation to provide optimal switching capability of the gate electrode.
With respect to claim 13, the combination of Kajiwara and Shirota discloses wherein the first concentration is less than 1×1016 cm−3.
However, it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the optimum concentration of the elements within the third electrode can be discovered by routine experimentation to provide optimal switching capability of the gate electrode.
With respect to claim 14, the combination of Kajiwara and Shirota discloses wherein the first insulating member includes a first insulating region [41a], a second insulating region [41b], and a third insulating region [41c], the first insulating region is provided between the third partial region and the first electrode region in the second direction, the second insulating region is provided between the first semiconductor portion and the first electrode region in the first direction, and the third insulating region is provided between the first electrode region and the second semiconductor portion in the first direction (see Kajiwara Figure 1).
With respect to claim 15, the combination of Kajiwara and Shirota discloses a first compound member [30] including Alz1Ga1-z1N (0<z 1≤1, x2<z1), the first compound member including a first compound region, and the first compound region being provided between the third partial region and the first insulating region (See Kajiwara ¶[0054]).
With respect to claim 16, the combination of Kajiwara and Shirota discloses wherein the first compound member further includes a second compound region and a third compound region, the second compound region is provided between the first semiconductor portion and the first insulating region, and the third compound region is provided between the third insulating region and the second semiconductor portion (See Kajiwara Figure 1).
With respect to claim 18, the combination of Kajiwara and Shirota discloses a second insulating member [42], the second insulating member including a first insulating portion [42a] and a second insulating portion [42b], the first semiconductor portion being provided between the fourth partial region and the first insulating portion in the second direction, and the second semiconductor portion being provided between the fifth partial region and the second insulating portion in the second direction (see Kajiwara Figure 1).
With respect to claim 19, the combination of Kajiwara and Shirota discloses wherein a part of the first electrode region is provided between the fourth partial region and the fifth partial region in the first direction (see Kajiwara Figure 1 and Shirota Figure 1(a)).
With respect to claim 20, the combination of Kajiwara and Shirota discloses wherein the first electrode is electrically connected to the first semiconductor portion, and the second electrode is electrically connected to the second semiconductor portion (see Kajiwara Figure 1).
Allowable Subject Matter
Claims 2-8 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 2-8 and 17, none of the prior art teaches or suggests, alone or in combination, the third electrode region includes the first element, or a third concentration of the first element in the third electrode region is higher than the first concentration.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyamoto et al. (U.S. Publication No. 2018/0026099 A1) discloses a HEMT but fails to disclose a third electrode region includes the first element, or a third concentration of the first element in the third electrode region is higher than the first concentration.
Hikita et al. (U.S. Patent No. 8,441,035 B2) discloses a AlGaN transistor device, but fails to disclose a third electrode region includes the first element, or a third concentration of the first element in the third electrode region is higher than the first concentration.
Tsuchiya et al. (U.S. Publication No. 2017/0301765 A1) discloses a HEMT but fails to disclose a third electrode region includes the first element, or a third concentration of the first element in the third electrode region is higher than the first concentration.
Neufeld et al. (U.S. Publication No. 2021/0043750 A1) discloses a HEMT but fails to disclose a third electrode region includes the first element, or a third concentration of the first element in the third electrode region is higher than the first concentration.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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