DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-5, 7-11, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. PGPub 2021/0407949) in view of Kim (U.S. PGPub 2021/0175134).
Regarding claim 1, Park teaches a semiconductor package (Figs. 1-3) comprising:
a semiconductor chip including a first surface and a second surface, which are opposite to each other in a first direction (210, [0020]-[0023]),
a plurality of first bumps in a first area on the first surface, the plurality of first bumps arranged along a second direction that intersects with the first direction (Figs. 1-2, CA, 290, [0018]), and
a plurality of second bumps in a second area on the first surface, the plurality of second bumps arranged along the second direction and spaced apart from the plurality of first bumps in a third direction that intersects with the first direction and the second direction (Figs. 1-2, EA, 195/290, [0018]).
Park does not explicitly teach a first test pad in a third area on the first surface between the first area and the second area, and a third bump on the first test pad, wherein the first test pad is along an edge of the semiconductor chip in the third direction.
Kim teaches a test pad along an edge of a semiconductor chip, where the test pad is located adjacent to and outside of a first area comprising bumps (Figs. 1-2, [0020], TB1, DB, [0026]), wherein a bump is on the test pad ([0026]), and wherein the test pad may be located in various areas on the chip (Figs. 7-9, [0045]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Park such that the device comprises a first test pad in a third area on the first surface between the first area and the second area, and a third bump on the first test pad, wherein the first test pad is along an edge of the semiconductor chip in the third direction for the purpose of providing testing pads for testing the package to increase reliability (Kim, [0042]-[0043]).
Regarding claim 4, the combination of Park and Kim teaches connection pads on the first surface, and through electrodes that extend into at least a portion of the semiconductor chip in the first direction, the through electrodes electrically connected to the connection pads (Park, 270, 250, [0041]). It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park and Kim for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Park and Kim teaches wherein the plurality of first bumps and the plurality of second bumps are on the connection pads, and are electrically connected to the connection pads and the through electrodes (Park, Fig. 2, [0040], [0055]). It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park and Kim for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Park and Kim teaches wherein upper surfaces of the plurality of first bumps, the plurality of second bumps and the third bump are an equal distance from the first surface of the semiconductor chip (Kim, Fig. 4). It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park and Kim for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Park and Kim teaches a plurality of fourth bumps in a fourth area on the first surface and arranged along the second direction and spaced apart from the plurality of second bumps in the third direction (Park, Figs. 1-2) but does not explicitly teach a second test pad in a fifth area between the second area and the fourth area, wherein the second test pad is along the edge of the semiconductor chip in the third direction. It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to further combine the teachings of Park and Kim for the reasons set forth in the rejection of claim 1.
Regarding claim 9, the combination of Park and Kim teaches wherein the semiconductor chip includes a first edge and a second edge, which extend in length in the second direction and are spaced apart from each other in the third direction, and a third edge and a fourth edge, which extend in length in the third direction and are spaced apart from each other in the second direction, and wherein the plurality of first bumps are along the first edge (Park, Fig. 1, left and right edges), and the plurality of fourth bumps are along the second edge (Kim, Fig. 1, device is rotated 90 degrees relative to Park). It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to further combine the teachings of Park and Kim for the reasons set forth in the rejection of claim 1.
Regarding claim 10, the combination of Park and Kim teaches wherein the third bump is between the plurality of first bumps and the plurality of second bumps along the third edge or the fourth edge but does not explicitly teach wherein a fifth bump is between the plurality of second bumps and the plurality of fourth bumps along the third edge or the fourth edge. It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to further combine the teachings of Park and Kim for the reasons set forth in the rejection of claim 1.
Regarding claim 11, Park teaches a semiconductor package (Figs. 1-3) comprising:
a semiconductor chip including a first surface and a second surface, which are opposite to each other in a first direction (210, [0020]-[0023]),
a first surface including a first area that extends in a third direction, a second area that extends in the third direction and is spaced apart from the first area in a second direction, a third area that extends in the third direction and is between the first area and the second area, wherein a second bump and a third bump are on the first surface in the second area and first area, respectively (Fig. 1, first/second areas are CA/EA, third area extends between, 290/195, [0018]).
Park does not explicitly teach a test pad on the first surface, a first bump on the test pad, wherein the second bump is spaced apart from the first bump in a second direction that intersects with the first direction and the third bump is spaced apart from the first bump in a direction opposite to the second direction, wherein the first bump is in the third area, and wherein the test pad is along an edge of the semiconductor chip in the second direction.
Kim teaches a test pad along an edge of a semiconductor chip, where the test pad is spaced apart from first bumps in a direction that intersects with the direction the bumps extend in (Figs. 1-2, [0020], TB1, DB, [0026]), wherein a bump is on the test pad ([0026]) and wherein the test pad may be located in various areas on the chip (Figs. 7-9, [0045]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Park such that the device comprises a test pad on the first surface, a first bump on the test pad, wherein the second bump is spaced apart from the first bump in a second direction that intersects with the first direction and the third bump is spaced apart from the first bump in a direction opposite to the second direction, wherein the first bump is in the third area, and wherein the test pad is along an edge of the semiconductor chip in the second direction for the purpose of providing testing pads for testing the package to increase reliability (Kim, [0042]-[0043]).
Regarding claim 16, Park teaches a semiconductor package (Figs. 1-3) comprising:
a base substrate (Fig. 12, 20, [0107]-[0110]),
a first semiconductor chip on the base substrate including a first surface facing the base substrate and a second surface opposite to the first surface in a first direction (110, [0020]-[0023]),
a plurality of second semiconductor chips on the first semiconductor chip, each second semiconductor chip including a third surface and a fourth surface opposite to the third surface in the first direction, the fourth surface at a level farther than the third surface from the base substrate in the first direction (210, [0020]-[0023], 310, [0062], Fig. 12), and
a first bump group between the base substrate and the first semiconductor chip, wherein the first bump group includes first bumps spaced apart from each other in a second direction that intersects with the first direction (Figs. 1-2, CA/EA, 290/195, [0018]).
Park does not explicitly teach a second bump between the first bumps, wherein the second bump is on a first test pad on the first surface, and wherein the first test pad is along an edge of the first semiconductor chip in the second direction.
Kim teaches a test pad along an edge of a semiconductor chip, where the test pad is located adjacent to and outside of a first area comprising bumps (Figs. 1-2, [0020], TB1, DB, [0026]), wherein a bump is on the test pad ([0026]), and wherein the test pad may be located in various areas on the chip (Figs. 7-9, [0045]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Park such that the device comprises a second bump between the first bumps, wherein the second bump is on a first test pad on the first surface, and wherein the first test pad is along an edge of the first semiconductor chip in the second direction for the purpose of providing testing pads for testing the package to increase reliability (Kim, [0042]-[0043]).
Regarding claim 17, the combination of Park and Kim teaches a second bump group between the first semiconductor chip and one of the second semiconductor chips or between a pair of second semiconductor chips, wherein the second bump group includes third bumps spaced apart from each other in the second direction (Park, Figs. 1-2) but does not explicitly teach a fourth bump between the third bumps, wherein the fourth bump is on a second test pad on the third surface, and wherein the second test pad is along an edge of a second semiconductor chip in the second direction. It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to further combine the teachings of Park and Kim for the reasons set forth in the rejection of claim 1.
Regarding claim 18, the combination of Park and Kim teaches a first adhesive layer between the base substrate and the first semiconductor chip, and a second adhesive layer between the first semiconductor chip and the second semiconductor chip or between each of second semiconductor chips, wherein the first adhesive layer surrounds sides of the first bumps and the second bump, and wherein the second adhesive layer surrounds sides of the third bumps and the fourth bump (140, 240, [0065]-[0066]).
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. PGPub 2021/0407949) in view of Kim (U.S. PGPub 2021/0175134) and Takahashi (U.S. PGPub 2015/0037914).
Regarding claim 2, the combination of Park and Kim does not explicitly teach wherein the first test pad is an electrical die sorting (EDS) test pad.
Takahashi teaches wherein test pads may be used for EDS and post-stacking tests ([0046], wafer testing).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Takahashi with Park and Kim such that the first test pad is an electrical die sorting (EDS) test pad for the purpose of using the test pads for electrical die sorting (Takahashi, [0046]).
Regarding claim 13, the combination of Park and Kim does not explicitly teach wherein the first test pad is an electrical die sorting (EDS) test pad.
Takahashi teaches wherein test pads may be used for EDS and post-stacking tests ([0046], wafer testing).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Takahashi with Park and Kim such that the first test pad is an electrical die sorting (EDS) test pad for the purpose of using the test pads for electrical die sorting (Takahashi, [0046]).
Claims 3 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. PGPub 2021/0407949) in view of Kim (U.S. PGPub 2021/0175134), Takahashi (U.S. PGPub 2015/0037914), and Das (U.S. PGPub 2019/0189576).
Regarding claim 3, the combination of Park, Kim, and Takahashi does not explicitly teach wherein the first test pad includes a third surface and a fourth surface, which are opposite to each other in the first direction, the third bump is on the third surface, and a test probing mark is on the third surface.
Das teaches wherein a test pad includes a top surface and a bottom surface, which are opposite to each other in the first direction, a bump is on the top surface, and a test probing mark is on the top surface (Figs. 6A-7B, 308, 312, 702, [0032]-[0034]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Das with Park, Kim, and Takahashi such that the first test pad includes a third surface and a fourth surface, which are opposite to each other in the first direction, the third bump is on the third surface, and a test probing mark is on the third surface for the purpose of preventing corrosion after wafer testing (Das, [0022]).
Regarding claim 14, the combination of Park, Kim, and Takahashi does not explicitly teach wherein the first test pad includes a third surface and a fourth surface, wherein the fourth surface is at a level farther than the third surface from the first surface in the first direction, the third bump is on the third surface, and a test probing mark is on the third surface.
Das teaches wherein a test pad includes a top surface and a bottom surface, wherein the top surface is farther from the chip surface in a first direction, a bump is on the top surface, and a test probing mark is on the top surface (Figs. 6A-7B, 308, 312, 702, [0032]-[0034]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Das with Park, Kim, and Takahashi such that the first test pad includes a third surface and a fourth surface, wherein the fourth surface is at a level farther than the third surface from the first surface in the first direction, the third bump is on the third surface, and a test probing mark is on the third surface for the purpose of preventing corrosion after wafer testing (Das, [0022]).
Regarding claim 15, the combination of Park, Kim, Takahashi, and Das teaches a seed layer between the test pad and the first bump, wherein the seed layer is in a portion of the test probing mark that extends into the test pad from the third surface of the test pad (Das, 506, [0032]-[0034]). It would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to further combine the teachings of Park, Kim, Takahashi, and Das for the reasons set forth in the rejection of claim 14.
Claims 6, 12, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. PGPub 2021/0407949) in view of Kim (U.S. PGPub 2021/0175134) and Kwon (U.S. PGPub 2024/0096841).
Regarding claim 6, Park and Kim do not explicitly teach wherein the third bump is electrically isolated from the first test pad.
Kwon teaches wherein a test pad may be electrically isolated from a test pad formed on the test pad ([0052]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kwon with Park and Kim such that the third bump is electrically isolated from the first test pad because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 12, Park and Kim do not explicitly teach wherein a length in the first direction from the first surface to an upper surface of the third bump is greater than a length in the first direction from the first surface to an upper surface of the first bump.
Kwon teaches wherein a length in the vertical direction from the surface of a semiconductor chip to an upper surface of a bump over a test pad is greater than a length in the vertical direction from the surface of the semiconductor chip to an upper surface of another bump (Fig. 2, 226/254, 230/240, [0037], [0047]-[0048]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kwon with Park and Kim such that a length in the first direction from the first surface to an upper surface of the third bump is greater than a length in the first direction from the first surface to an upper surface of the first bump because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 19, Park and Kim do not explicitly teach wherein the fourth bump is electrically isolated from the first semiconductor chip and the second semiconductor chip.
Kwon teaches wherein a test pad may be electrically isolated from a test pad formed on the test pad ([0052]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kwon with Park and Kim such that the fourth bump is electrically isolated from the first semiconductor chip and the second semiconductor chip because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 20, Park and Kim do not explicitly teach wherein the second bump is electrically isolated from the base substrate and the first semiconductor chip.
Kwon teaches wherein a test pad may be electrically isolated from a test pad formed on the test pad ([0052]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kwon with Park and Kim such that the second bump is electrically isolated from the base substrate and the first semiconductor chip because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
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