DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 22, 24, and 25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 10, and 15 of U.S. Patent No. 12,010,871. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent recite each limitation of the instant application as shown below.
18/671,060
12,010,871
21. A thin film transistor comprising:
a first gate electrode;
an oxide semiconductor layer including indium and gallium;
a first insulating layer between the first gate electrode and the oxide semiconductor layer on the first gate electrode side, the first insulating layer including silicon nitride;
a second insulating layer between the first gate electrode and the oxide semiconductor layer on the oxide semiconductor layer side, the second insulating layer including silicon oxide;
a second gate electrode on an opposite side of the oxide semiconductor layer from the first gate electrode;
a third insulating layer between the second gate electrode and the oxide semiconductor layer on the second gate electrode side, the third insulating layer including silicon nitride; and
a fourth insulating layer between the second gate electrode and the oxide semiconductor layer on the oxide semiconductor layer side, the fourth insulating layer including silicon oxide, wherein
a total thickness of the first insulating layer and the second insulating layer is greater than a total thickness of the third insulating layer and the fourth insulating layer.
1. A thin film transistor comprising: an active layer formed of an oxide semiconductor including at least indium and gallium; a gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side; a second gate electrode provided on an opposite side of the active layer from the gate electrode; a third gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; and a fourth gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is greater than a total thickness of the third gate insulating layer and the fourth gate insulating layer.
6. The thin film transistor according to claim 1, wherein the first gate insulating layer and the third gate insulating layer are silicon nitride layers, the second gate insulating layer and the fourth gate insulating layer are silicon oxide layers, the second gate insulating layer is thicker than the first gate insulating layer, and the fourth gate insulating layer is thicker than the third gate insulating layer.
22. The thin film transistor according to claim 21, wherein a thickness of the second insulating layer is greater than a thickness of the first insulating layer, and a thickness of the fourth insulating layer is greater than a thickness of the third insulating layer.
6. The thin film transistor according to claim 1, wherein the first gate insulating layer and the third gate insulating layer are silicon nitride layers, the second gate insulating layer and the fourth gate insulating layer are silicon oxide layers, the second gate insulating layer is thicker than the first gate insulating layer, and the fourth gate insulating layer is thicker than the third gate insulating layer.
24. A display device comprising:
a pixel, the pixel comprising:
a thin film transistor; and
a pixel electrode connected to the thin film transistor;
the thin film transistor includes:
a first gate electrode;
an oxide semiconductor layer including indium and gallium;
a first insulating layer between the first gate electrode and the oxide semiconductor layer on the first gate electrode side, the first insulating layer including silicon nitride;
a second insulating layer between the first gate electrode and the oxide semiconductor layer on the oxide semiconductor layer side, the second insulating layer including silicon oxide;
a second gate electrode on an opposite side of the oxide semiconductor layer from the first gate electrode;
a third insulating layer between the second gate electrode and the oxide semiconductor layer on the second gate electrode side, the third insulating layer including silicon nitride; and
a fourth insulating layer between the second gate electrode and the oxide semiconductor layer on the oxide semiconductor layer side, the fourth insulating layer including silicon oxide, wherein
a total thickness of the first insulating layer and the second insulating layer is greater than a total thickness of the third insulating layer and the fourth insulating layer.
10. A display device having a pixel, the pixel comprising: a thin film transistor; and a pixel electrode connected to the thin film transistor, wherein the thin film transistor includes: an active layer formed of an oxide semiconductor including at least indium and gallium; at least one gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side; a second gate electrode provided on an opposite side of the active layer from the gate electrode; a third gate insulating layer provided between the active layer and the gate electrode on the gate electrode side; and a fourth gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is greater than a total thickness of the third gate insulating layer and the fourth gate insulating layer.
15. The display device according to claim 10, wherein the first gate insulating layer and the third gate insulating layer are silicon nitride layers, the second gate insulating layer and the fourth gate insulating layer are silicon oxide layers, the second gate insulating layer is thicker than the first gate insulating layer, and the fourth gate insulating layer is thicker than the third gate insulating layer.
25. The display device according to claim 24, wherein a thickness of the second insulating layer is greater than a thickness of the first insulating layer, and a thickness of the fourth insulating layer is greater than a thickness of the third insulating layer.
15. The display device according to claim 10, wherein the first gate insulating layer and the third gate insulating layer are silicon nitride layers, the second gate insulating layer and the fourth gate insulating layer are silicon oxide layers, the second gate insulating layer is thicker than the first gate insulating layer, and the fourth gate insulating layer is thicker than the third gate insulating layer.
Allowable Subject Matter
Claims 23 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2016/0155759 to Yamazaki et al. teach a thin film transistor having an oxide semiconductor including indium and gallium, two gate electrodes and four insulating layers comprising silicon oxide and silicon nitride. Yamazaki et al. do not teach a total thickness of the first insulating layer and the second insulating layer is greater than a total thickness of the third insulating layer and the fourth insulating layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897