DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 1-3, 5-9, is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEZUKA et al., US 2016/0225795 A1.
Claims 1, 7. KOEZUKA et al., disclose a display device (such as the one in figs. 9, 19 and 20) comprising:
-a first conductive layer (item 104);
-a first insulating film (item 106) arranged on the first conductive layer;
-an oxide semiconductor layer (item 108) arranged on the first insulating film;
-a second conductive layer (item 112) arranged on the first insulating film and connected to the oxide semiconductor layer.
In the embodiment of FIG. 9, KOEZUKA appears not to explicitly disclose all the limitations as in claim 1.
However, in other embodiments (such as the embodiment of FIG. 20) KOEZUKA discloses:
-a planarization layer (item 770) arranged on the oxide semiconductor layer (item 767);
-a first transparent conductive layer (item 784) in contact with the second conductive layer (item 788) inside an opening in the planarization layer;
-and a second transparent conductive layer in contact with the first transparent conductive layer inside the opening (this limitation would read through [0337], wherein is disclosed an alignment film may be provided on each of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776).
To improve quality of a display device, it would have been obvious to one of ordinary skill in the art at the time of invention to use a transparent conductive material in the planarization layer that is beneficial when the layer needs to be both electrically conductive and optically transparent, enabling smooth surface formation while preserving display performance. This is especially important in modern transparent and non-backlit displays where electrode transparency is essential.
Claim 2. KOEZUKA et al., disclose the display device according to claim 1, wherein the first transparent conductive layer is an oxide conductive layer (this limitation would read through [0256], wherein is disclosed that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity).
Claim 3. KOEZUKA et al., disclose the display device according to claim 1, wherein the display device further comprises a nitride insulating layer arranged on the planarization layer, and the first conductive layer is in contact with the nitride insulating layer (this limitation would read through [0323], wherein is disclosed that the insulating films 764, 766, and 768, an oxide semiconductor film 767, and a planarization insulating film 770 are formed over the transistor 750, the transistor 752, and the capacitor 790).
Claims 5-6. KOEZUKA et al., disclose the display device according to claim 1, wherein the first transparent conductive layer is in contact with the second conductive layer inside the opening via a third transparent conductive layer (this limitation would read through [0074], wherein is disclosed that the oxide semiconductor film 108 includes a first oxide semiconductor film 108a on the conductive film 104 side and a second oxide semiconductor film 108b over the first oxide semiconductor film 108a. Note that the conductive film 104 functions as a gate electrode. Furthermore, the insulating films 106 and 107 function as gate insulating films of the transistor 100).
Claim 8. KOEZUKA et al., disclose the display device according to claim 7, wherein the oxide semiconductor layer is in contact with the first transparent conductive layer inside the opening (this limitation would read through [0337], wherein is disclosed an alignment film may be provided on each of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776).
Claim 9. KOEZUKA et al., disclose the display device according to claim 7, wherein the display device further comprises a second transparent conductive layer in contact with the oxide semiconductor layer inside the opening, and the second transparent conductive layer is in contact with the first transparent conductive layer inside the opening (this limitation would read through [0337], wherein is disclosed an alignment film may be provided on each of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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