DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because of the following: lines 7 – 8 recite “a device may include the capacitor array includes at least a first and second capacitor array,” which appear to contain a grammatical error. Examiner instead suggests “a device may include the capacitor array which includes at least a first and second capacitor array,” or something similar. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claim 11 is objected to because of the following informality: line 11 of claim 11 recites “the voltage regulator and the load.” However, in previous recitations, it is recited “the voltage regulator or a load.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)a(1) as being anticipated by Himeda et al. (US Patent No. 11,121,123).
Regarding claim 1, in Figure 16, Himeda discloses a module configured for a semiconductor composite apparatus in which a direct current voltage adjusted by a voltage regulator including a semiconductor active element is supplied to a load, the module comprising: a capacitor array (210A, 210B) that is configured with a plurality of capacitor portions (234, 232, Figure 3) disposed in a plane; a through-hole conductor (268, Figure 15) that penetrates the plurality of capacitor portions in a thickness direction of the capacitor array and provides an electrical connection between the plurality of capacitor portions (portions 234, 232 of capacitor array 210A is electrically connected to portions 234, 232 of capacitor array 210B) and at least one of the voltage regulator and the load (300); and a connection terminal layer (205, Figure 12(a)) electrically connected to the through-hole conductor and is used for electrical connection between the plurality of capacitor portions and at least one of the voltage regulator and the load (300), wherein the capacitor array includes at least a first capacitor array (210A) and a second capacitor array (210B), and, when viewed from a mounting surface of the connection terminal layer, at least a part of the first capacitor array overlaps at least a part of the second capacitor array (Figure 16).
Regarding claim 2, Himeda discloses wherein a difference between a withstanding voltage of the first capacitor array and a withstanding voltage of the second capacitor array is 1 V or greater (Figure 16).
Regarding claim 3, Himeda discloses wherein: the capacitor array further includes a third capacitor array, and when viewed from the mounting surface of the connection terminal layer, at least a part of the first capacitor array, at least a part of the second capacitor array, and at least a part of the third capacitor array overlap each other (Figure 16).
Regarding claim 4, Himeda discloses semiconductor composite apparatus comprising: the module according to claim 1; the voltage regulator; and the load (Figure 16).
Regarding claim 5, Himeda discloses wherein, when viewed from the mounting surface of the connection terminal layer, at least a part of the semiconductor active element included in the voltage regulator overlaps the first capacitor array and the second capacitor array (Figure 16).
Regarding claim 6, Himeda discloses wherein, when viewed from the mounting surface of the connection terminal layer, at least a part of the first capacitor array and at least a part of the second capacitor array overlap the load (Figure 16).
Regarding claim 7, Himeda discloses a wiring board that is electrically connected to the voltage regulator and the load (Figure 16).
Regarding claim 8, Himeda discloses wherein one of the first capacitor array and the second capacitor array is on a mounting surface of the wiring board, and another of the first capacitor array and the second capacitor array is in the wiring board (Figure 16).
Regarding claim 9, Himeda discloses wherein: the wiring board includes a first wiring board and a second wiring board, the first capacitor array is in the first wiring board, and the second capacitor array is in the second wiring board (Figure 16).
Regarding claim 10, Himeda discloses wherein: the capacitor array further includes a third capacitor array, the first capacitor array is on one mounting surface of the wiring board, the second capacitor array is in the wiring board, and the third capacitor array is on another mounting surface of the wiring board (Figure 16).
Regarding claim 11, in Figure 16, Himeda discloses a module configured for a semiconductor composite apparatus, the module comprising: a capacitor array (210A, 210B) including a first array (210A) and a second array (210B) including a plurality of capacitor portions (234, 232; Figure 3) disposed in a plane; a through-hole conductor (268, Figure 15) that penetrates the plurality of capacitor portions in a thickness direction of the capacitor array and provides an electrical connection between the plurality of capacitor portions (portions 234, 232 of capacitor array 210A is electrically connected to portions 234, 232 of capacitor array 210B) and a voltage regulator or a load (300); a connection terminal layer (205, Figure 12(a)) that is electrically connected to the through-hole conductor and that provides an electrical connection between the plurality of capacitor portions and the voltage regulator or the load (300); and a wiring board (200, Figure 3; or 400, Figure 15) configured to be connected to the voltage regulator and the load (300); wherein, when the capacitor array is viewed from a mounting surface of the connection terminal layer, at least a portion of the first array overlaps at least a portion of the second array (Figure 16), and wherein the first array or the second array are disposed on a mounting surface of the wiring board (400, Figure 15).
Regarding claim 12, Himeda discloses wherein the first array or the second array are disposed in the wiring board (Figure 16).
Regarding claim 13, Himeda discloses wherein a difference between a withstanding voltage of the first array and a withstanding voltage of the second array is 1V or greater (Figure 16).
Regarding claim 14, Himeda discloses wherein: the capacitor array further includes a third array, and when viewed from the mounting surface of the connection terminal layer, a portion of the first array, a portion of the second array, and a portion of the third array overlap each other (Figure 16).
Regarding claim 15, in Figure 16, Himeda discloses a semiconductor composite apparatus comprising: a voltage regulator (100, Figure 3); a load (300); a capacitor array (210A, 210B) including a first array and a second array including a plurality of capacitor portions (234, 232, Figure 3) disposed in a plane; a through-hole conductor (268, Figure 15) that penetrates the plurality of capacitor portions in a thickness direction of the capacitor array and that provides an electrical connection between the plurality of capacitor portions (portions 234, 232 of capacitor array 210A is electrically connected to portions 234, 232 of capacitor array 210B) and the voltage regulator or the load (300); a connection terminal layer (205, Figure 12(a)) electrically connected to the through-hole conductor and that provides an electrical connection between the plurality of capacitor portions and the voltage regulator or the load (300); and a wiring board (200, Figure 3 OR 400, Figure 15) configured to be connected to the voltage regulator and the load; wherein, when the capacitor array is viewed from a mounting surface of the connection terminal layer, at least a portion of the first array overlaps at least a portion of the second array (Figure 16), and wherein the first array or the second array are disposed on a mounting surface of the wiring board (Figure 15).
Regarding claim 16, Himeda discloses wherein the first array or the second array are disposed in the wiring board (Figure 16).
Regarding claim 17, Himeda discloses wherein, when viewed from the mounting surface of the connection terminal layer, a part of a semiconductor active element included in the voltage regulator overlaps the first array or the second array (Figure 16).
Regarding claim 18, Himeda discloses wherein, when viewed from the mounting surface of the connection terminal layer, a part of the first array or a part of the second array overlap the load (Figure 16).
Regarding claim 19, Himeda discloses wherein a difference between a withstanding voltage of the first array and a withstanding voltage of the second array is 1 V or greater (Figure 16).
Regarding claim 20, Himeda discloses wherein: the capacitor array further includes a third array, and when viewed from the mounting surface of the connection terminal layer, a portion of the first array, a portion of the second array, and a portion of the third array overlap each other (Figure 16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847