Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18/671,215 filed on September 03, 2026.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Device Comprising Multiple Signal Line Layers Separated Through Insulating Film Layer a.
Election/Restrictions
6. Applicant’s election without traverse of claims 1-11, Group I, drawn to device, in the reply filed on 09/03/2026 is acknowledged.
7. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected method device claims, Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/22/2026.
Claim Objections
8. Claims 1, 4, 5 are objected to because of the following informalities: In the following, the claims should be recited to fix typos, and/or smooth flow of claim languages/phrases:
1. (Currently Amended) A semiconductor device, comprising a substrate and at least one functional layer, wherein each functional layer comprises:
a first signal line layer and a second signal line layer, stacked on the substrate in a vertical direction, wherein the first signal line layer comprises a plurality of first signal lines spaced apart, and the second signal line layer comprises a plurality of second signal lines spaced apart, the second signal line layer is located by a side of the first signal line layer away from the substrate and insulated from the second signal line layer by an insulation film layer, and each first signal line of the plurality of first signal lines and each second signal line of the plurality of second signal lines extends in a first horizontal direction;
wherein each first signal line and each second signal line have a body extension portion and a lead-out end, and for each first signal line and each second signal line, the lead-out end is located at
wherein an orthographic projection of the body extension portion of each first signal line overlaps with an orthographic projection of the body extension portion of each second signal line on the substrate; and
wherein orthographic projections of the lead-out end of each first signal line and the lead-out end of each second signal line on the substrate are non-overlapping.
4. (Currently Amended) The semiconductor device according to claim 2, wherein each functional layer further comprises:
a third signal line layer with a plurality of third signal lines spaced apart extending in a second horizontal direction, wherein the third signal line layer is stacked with the first signal line layer and the second signal line layer in the vertical direction, and is insulated from adjacent signal line layers of the third signal line layer by insulation film layers, and the second horizontal direction is intersected with the first horizontal direction;
wherein each third signal line has a body extension portion and a lead-out end, wherein the lead-out end of each third signal line is located at
5. (Currently Amended) The semiconductor device according to claim 4, wherein each functional layer further comprises:
a fourth signal line layer with a plurality of four signal lines spaced apart extending in the second horizontal direction, wherein the fourth signal line layer is stacked with the first signal line layer, the second signal line layer and the third signal line layer in the vertical direction, and is insulated from adjacent signal line layers of the fourth signal line layer by the insulation film layer,
wherein each fourth signal line has a body extension portion and a lead-out end, wherein the lead-out end of each fourth signal line is located at
wherein an orthographic projection of the body extension portion of each fourth signal line overlaps with an orthographic projection of the body extension portion of each third signal line on the substrate; and
wherein orthographic projections of the lead-out end of each fourth signal line and the lead-out end of each third signal line on the substrate are non-overlapping.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 1-8, 10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yang (US 2023/0033311 A1).
Regarding independent claim 1, Yang teaches a semiconductor device (Fig. 3J), comprising a substrate (100, para [0015]) and at least one functional layer (1st and 2nd signal lines, see the annotated figure below), wherein each functional layer comprises:
a first signal line layer (COA contact, see 1st signal line in the annotated figure below) and a second signal line layer (see the annotated figure below), stacked on the substrate (100) in a vertical direction (y-direction), wherein the first signal line layer (COA contact) comprises a plurality of first signal lines (COA contact, left segment and right segment) spaced apart, and the second signal line layer (see the annotated figure below) comprises a plurality of second signal lines (2nd signal lines, left segment and right segment) spaced apart, the second signal line layer is located by a side of the first signal line layer (COA contact) away from the substrate (100) and insulated from the second signal line layer by an insulation film layer (116, para [0028]), and each first signal line and each second signal line extends in a first horizontal direction (x- direction);
wherein each first signal line (1st signal line, left segment/right segment) and each second signal line (2nd signal line, left segment /right segment) have a body extension portion (see the annotated figure below) and a lead-out end (top ends), and for each first signal line (1st signal line, left segment /right segment) and each second signal line (2nd signal line, left segment /right segment), the lead-out end is located at least one end of the body extension portion (vertical segment) in the first horizontal direction;
wherein an orthographic projection (overlapped vertical projection) of the body extension portion (1st body extension) of each first signal line (1st signal line) overlaps with an orthographic projection (overlapped vertical projection) of the body extension portion of each second signal line (2nd signal line) on the substrate (100); and
wherein orthographic projections (overlapped vertical projections) of the lead-out end of each first signal line (1st signal line) and the lead-out end of each second signal line (2nd signal line) on the substrate (100) are non-overlapping (because of vertical alignment).
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Regarding claim 2, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1), for each first signal line (1st signal line) and each second signal line (2nd signal line), the lead-out end has a first surface (bottom end) close to the substrate (100) and a second surface (upper or top end) away from the substrate (100); and
wherein for each first signal line (1st signal line) and each second signal line (2nd signal line), a direction (horizontal) of the first surface pointing to the second surface or a direction (horizontal) of the second surface pointing to the first surface is a lead-out direction (horizontal).
Regarding claim 3, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1):
when the direction (horizontal) of the second surface pointing to the first surface is the lead-out direction (horizontal), an extension length (horizontal length of 1st signal line) of each first signal line is less (see figure in claim 1) than an extension length (horizontal length of 2nd signal line) of each second signal line in a same functional layer; or
when the direction of the first surface pointing to the second surface is the lead- out direction, the extension length of each second signal line is less than the extension length of each first signal line in a same functional layer.
Regarding claim 4, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1): each functional layer further comprises:
a third signal line layer (3rd signal line) with a plurality of third signal lines (left segment and right segment) spaced apart extending in a second horizontal direction (x- direction), wherein the third signal line layer (3rd signal line) is stacked with the first signal line layer (1st signal line) and the second signal line layer (2nd signal line) in the vertical direction, and is insulated from adjacent signal line layers of the third signal line layer by insulation film layers (105a, para [0023]), and the second horizontal direction is intersected with the first horizontal direction;
wherein each third signal line (3rd signal line) has a body extension portion (vertical segment, see the annotated figure in claim 1) and a lead-out end (end of the body extension), wherein the lead-out end of each third signal line (3rd signal line) is located at least one end of the body extension portion of each third signal line (3rd signal line) in the second horizontal direction.
Regarding claim 5, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1): each functional layer further comprises:
a fourth signal line layer (4th signal line) with a plurality of four signal lines (left segment and right segment) spaced apart extending in the second horizontal direction, wherein the fourth signal line layer (4th signal line) is stacked with the first signal line layer (1st signal line), the second signal line layer (2nd signal line) and the third signal line layer (3rd signal line) in the vertical direction, and is insulated from adjacent signal line layers of the fourth signal line layer (4th signal line) by the insulation film layer (116),
wherein each fourth signal line (4th signal line) has a body extension portion (vertical segment, shown in the figure of claim 1) and a lead-out end (end of the vertical segment), wherein the lead-out end of each fourth signal line (4th signal line) is located at least one end of the body extension portion of each fourth signal line (4th signal line) in the second horizontal direction;
wherein an orthographic projection (overlapped vertical projection) of the body extension portion of each fourth signal line (4th signal line) overlaps with an orthographic projection (overlapped vertical projection) of the body extension portion of each third signal line (3rd signal line) on the substrate (100); and
wherein orthographic projections of the lead-out end of each fourth signal line (4th signal line) and the lead-out end of each third signal line (3rd signal line) on the substrate (100) are non-overlapping (because of vertical alignment).
Regarding claim 6, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1): in each functional layer, the third signal line layer (3rd signal line) is formed between the first signal line layer (1st signal line) and the second signal line layer (2nd signal line),
wherein in each functional layer, the fourth signal line layer (4th signal line) is formed between the third signal line layer (3rd signal line) and the second signal line layer (2nd signal line); or
wherein in each functional layer, the fourth signal line layer is formed by a side of the second signal line layer away from the third signal line layer.
Regarding claim 7, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1): the lead-out end (top end) of each third signal line (3rd signal line) and each fourth signal line (4th signal line) have a first surface (bottom surface) close to the substrate (100) and a second surface (upper surface) away from the substrate (100);
wherein for each third signal line (3rd signal line) and each fourth signal line (4th signal line), a direction of the first surface pointing to the second surface or a direction of the second surface pointing to the first surface is the lead-out direction.
Regarding claim 8, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1):
when the direction of the second surface pointing to the first surface is the lead- out direction, an extension length (horizontal length/distance) of each third signal line (3rd signal line) is less than an extension length (horizontal length/distance) of each fourth signal line (4th signal line) in a same functional layer; or
when the direction of the first surface pointing to the second surface is the lead- out direction, an extension length of each fourth signal line is less than an extension length of each third signal line in a same functional layer.
Regarding claim 10, Yang teaches wherein (Fig. 3J: see the annotated figure in claim 1): a plurality of functional layers (1st, 2nd, 3rd, 4th signal lines) are sequentially stacked on the substrate (100) in the vertical direction;
wherein in two adjacent functional layers (2nd and 1st signal lines), when the direction of the second surface pointing to the first surface is the lead-out direction, an extension length (horizontal length/distance) of each first signal line (1st signal line) in a functional layer away from the substrate (100) is greater than an extension length (horizontal length/distance) of each second signal line in a functional layer close to the substrate (100), and a length of each third signal line in the functional layer away from the substrate (100) is greater than a length of each fourth signal line in the functional layer close to the substrate (100); or
when the direction of the first surface pointing to the second surface is the lead- out direction, the extension length of each first signal line in the functional layer away from the substrate is less than the extension length of each second signal line in the functional layer close to the substrate, and the length of each third signal line in the functional layer away from the substrate is less than the length of each fourth signal line in the functional layer close to the substrate.
Allowable Subject Matter
12. Claims 9, 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor device, comprising:
…. further comprising a first lead-out structure, a second lead-out structure, a third lead-out structure and a fourth lead-out structure spaced apart from each other, wherein the first lead-out structure, the second lead-out structure, the third lead-out structure and the fourth lead-out structure extend in the vertical direction and have different extension lengths;
wherein one end of the first lead-out structure is in contact with the lead-out end of each first signal line, and another end of the first lead-out structure extends in the lead-out direction and passes through each insulation film layer;
wherein one end of the second lead-out structure is in contact with the lead-out end of each second signal line, and another end of the second lead-out structure extends in the lead-out direction and passes through each insulation film layer;
wherein one end of the third lead-out structure is in contact with the lead-out end of each third signal line, and another end of the third lead-out structure extends in the lead-out direction and passes through each insulation film layer;
wherein one end of the fourth lead-out structure is in contact with the lead-out end of each fourth signal line, and another end of the fourth lead-out structure extends in the lead-out direction and passes through each insulation film layer; and
wherein each functional layer has the first lead-out structure, the second lead-out structure, the third lead-out structure and the fourth lead-out structure.
Claim 11: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor device, comprising:
…. wherein each functional layer further comprises a first transistor structure and a second transistor structure stacked sequentially in the vertical direction, and each of the first transistor structure and the second transistor structure comprises a gate region, a first connection region and a second connection region;
wherein the first connection region of the first transistor structure is connected to the body extension portion of each first signal line, the second connection region of the first transistor structure is connected to the body extension portion of each third signal line, the first connection region of the second transistor structure is connected to the gate region of the first transistor structure, the second connection region of the second transistor structure is connected to the body extension portion of each second signal line, and the gate region of the second transistor structure is connected to the body extension portion of each fourth signal line.
10. Prior arts made of record in PTO-892 and not relied upon are considered pertinent to applicant’s disclosure: Yang (US 2023/0033311 A1) is a close prior art that describes in Fig. 3J, a three dimensional memory arrangement structure on the substrate and comprises horizontal stack gate (GL) layers 120 which are connected with respective vertical contacts COA, however, Yang does not show different lead-out structures spaced apart from each other; and the functional layer comprises different transistor structures stacked in the vertical direction, therefore, either by itself or in combination with other arts fail to disclose the above quoted limitation in section 7.
Examiner’s Note
12. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
14. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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