DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 5 refers to the first, second, third, fourth, fifth, and sixth electrodes. No antecedent basis is provided for the first through fourth electrodes in claim 5 or the claims from which it depends. For purposes of examination, in light of the disclosure, claim 5 will be interpreted to additionally recite that the first bare die has first and third electrodes and the second bare die has second and fourth electrodes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 11, and 14-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ohguro (U.S. PGPub 2022/0084917).
Regarding claim 1, Ohguro teaches a chip package module (Figs. 1-6), comprising:
a first conductive frame (110, Fig. 2, [0043]),
a first bare die disposed on the first conductive frame (140, [0046], Figs. 4-5)
a second conductive frame disposed at an interval from the first conductive frame (120, [0044], Fig. 2),
a first conductive connecting sheet, connected to a surface of the first bare die away from the first conductive frame, and extending to be lapped on the second conductive frame (160, [0053], Fig. 3),
a second bare die, laminated on the surface of the first bare die away from the first conductive frame, and connected to the first conductive connecting sheet (150, [0050]), and
a conductive cover plate, connected to a surface of the second bare die away from the first conductive frame, and extending to be connected to the first conductive frame (180, [0064], Fig. 6A).
Regarding claim 2, Ohguro teaches wherein
a first electrode of the first bare die is electrically connected to the first conductive frame (143, [0047]), and a second electrode of the second bare die is electrically connected to the conductive cover plate, to implement an electrical connection between the first electrode and the second electrode (153, [0051], [0063], Fig. 6A),
both a third electrode of the first bare die and a fourth electrode of the second bare die are electrically connected to the first conductive connecting sheet, to implement an electrical connection between the third electrode and the fourth electrode (Fig. 4, 141/151, [0053]).
Regarding claim 3, Ohguro teaches wherein the chip package module further comprises a third conductive frame and a second conductive connecting sheet (130, Fig. 2, [0045]; 170, [0038], Fig. 5) and the first conductive frame, the second conductive frame, and the third conductive frame are disposed at an interval from each other (Fig. 2) and
the second conductive connecting sheet is connected to the surface of the first bare die away from the first conductive frame, and extends to be lapped on the third conductive frame, and the second conductive connecting sheet is disposed at an interval from the first conductive connecting sheet (Fig. 3, [0055]).
Regarding claim 4, Ohguro teaches wherein both a fifth electrode of the first bare die and a sixth electrode of the second bare die are electrically connected to the second conductive connecting sheet, to implement an electrical connection between the fifth electrode and the sixth electrode (Fig. 5, 142/152, [0058]).
Regarding claim 5, Ohguro teaches wherein the first bare die comprises a first electrode and a third electrode and the second bare die comprises a second electrode and a fourth electrode (141/143, 151/153, Figs. 4-5), wherein the first electrode is a first source, the third electrode is a first drain, the fifth electrode is a first gate, the second electrode is a second source, the fourth electrode is a second drain, and the sixth electrode is a second gate ([0047], [0051]-[0060]),
the first source, the first drain, and the first gate are electrically connected in a one-to-one correspondence to the first conductive frame, the first conductive connecting sheet, and the second conductive connecting sheet; and the second source, the second drain, and the second gate are electrically connected in a one-to-one correspondence to the conductive cover plate, the first conductive connecting sheet, and the second conductive connecting sheet (Figs. 3-5, [0047], [0051]-[0060], [0063]).
Regarding claim 6, Ohguro teaches wherein the first source is connected in parallel to the second source, the first drain is connected in parallel to the second drain, and the first gate is connected in parallel to the second gate ([0086]).
Regarding claim 7, Ohguro teaches wherein the first drain is electrically connected to the first conductive frame, the first gate is electrically connected to the first conductive connecting sheet, and the first source is electrically connected to the second conductive connecting sheet; and the second drain is electrically connected to the conductive cover plate, the second gate is electrically connected to the first conductive connecting sheet, and the second source is electrically connected to the second conductive connecting sheet ([0047], [0051]-[0060]).
Regarding claim 8, Ohguro teaches wherein the conductive cover plate comprises a flat plate and at least one side plate that is bent and connected to the flat plate, the flat plate covers the surface of the second bare die away from the first conductive frame, and each side plate is connected between the flat plate and the first conductive frame (Figs. 1 and 6A, 181/183, [0064]).
Regarding claim 9, Ohguro teaches wherein each side plate is vertically connected to the flat plate (Figs. 1 and 6A, 181/183, [0064]).
Regarding claim 11, Ohguro teaches wherein solder is disposed between the first bare die and the first conductive frame, and an electrical connection is implemented by soldering (143a, [0047], [0083]),
solder is disposed in regions in which the first conductive connecting sheet is lapped on the first bare die and the second conductive frame, and the first conductive connecting sheet is electrically connected to the first bare die and the second conductive frame by soldering (141a, 123, [0055]-[0056], [0083]),
solder is disposed in a region in which the second bare die is lapped on the first conductive connecting sheet, and the second bare die is electrically connected to the first conductive connecting sheet by soldering (151a, [0055], [0083]) and
solder is disposed between the conductive cover plate and the second bare die, and the conductive cover plate is electrically connected to the second bare die by soldering (153a, [0065], [0083]).
Regarding claim 14, Ohguro teaches a method, comprising:
providing a first conductive frame and a second conductive frame, wherein the second conductive frame is disposed at an interval beside the first conductive frame (110, 120, [0076], Fig. 7A),
attaching a first bare die to the first conductive frame (140, [0076], Fig. 7A),
arranging a first conductive connecting sheet, wherein the first conductive connecting sheet is connected to a surface of the first bare die away from the first conductive frame, and extends to be lapped on the second conductive frame (160, Figs. 8A and 4, [0078]),
attaching a second bare die to the surface of the first bare die away from the first conductive frame, wherein the second bare die is connected to the first conductive connecting sheet (150, Fig. 9B, [0080]),
arranging a conductive cover plate, wherein the conductive cover plate is connected to a surface of the second bare die away from the first conductive frame, and extends to be connected to the first conductive frame (180, Fig. 10B, [0082]).
Regarding claim 15, Ohguro teaches before the second bare die is arranged, providing a third conductive frame located at an interval beside the first conductive frame (130, [0077], Fig. 7A); and
arranging a second conductive connecting sheet, wherein the second conductive connecting sheet is connected to the surface of the first bare die away from the first conductive frame and extends to be lapped on the third conductive frame, and the second conductive connecting sheet is disposed at an interval from the first conductive connecting sheet (170, Figs. 8A-8B, [0078]).
Regarding claim 16, Ohguro teaches wherein the conductive cover plate comprises a flat plate and at least one side plate that is bent and connected to the flat plate, the flat plate covers the surface of the second bare die away from the first conductive frame, and each side plate is connected between the flat plate and the first conductive frame (Figs. 10A and 6A, 181/183, [0064], [0082]).
Regarding claim 17, Ohguro teaches wherein each of the first bare die and the second bare die comprises a plurality of electrodes, the plurality of electrodes of the first bare die comprise a source, a drain, and a gate, and the plurality of electrodes of the second bare die also comprise a source, a drain, and a gate ([0047], [0052]),
the source, the drain, and the gate of the first bare die are electrically connected in a one-to-one correspondence to the first conductive frame, the first conductive connecting sheet, and the second conductive connecting sheet ([0047], [0054], [0058]),
the source, the drain, and the gate of the second bare die are electrically connected in a one-to-one correspondence to the conductive cover plate, the first conductive connecting sheet, and the second conductive connecting sheet ([0054], [0058], [0063]), and
the source of the first bare die is connected in parallel to the source of the second bare die, the drain of the first bare die is connected in parallel to the drain of the second bare die, and the gate of the first bare die is connected in parallel to the gate of the second bare die ([0086]).
Regarding claim 18, Ohguro teaches wherein attaching the first bare die to the first conductive frame comprises: arranging solder on the first conductive frame, placing the first bare die on the solder, and then electrically connecting the first bare die to the first conductive frame by soldering ([0076], [0083])
arranging the first conductive connecting sheet and arranging a second conductive connecting sheet comprises:
arranging two groups of solder disposed at intervals on the surface of the first bare die away from the first conductive frame, arranging solder separately on the second conductive frame and the third conductive frame (Fig. 7A, 141aF, 142aF, 123F, 133F, [0077]), then placing the first conductive connecting sheet on one group of solder of the first bare die and the solder on the second conductive frame (160, Fig. 8A, [0078]),
arranging the second conductive connecting sheet on the other group of solder of the first bare die and the solder on the third conductive frame, and electrically connecting the first conductive connecting sheet to the first bare die and the second conductive frame by soldering and electrically connecting the second conductive connecting sheet to the first bare die and the third conductive frame by soldering (170, Fig. 8A, [0078], [0083]),
attaching the second bare die comprises: separately arranging solder on surfaces of the first conductive connecting sheet and the second conductive connecting sheet away from the first bare die (Fig. 8A, 151aF, 152aF, [0079]), placing the second bare die on the solder, and electrically connecting the second bare die to the first conductive connecting sheet and the second conductive connecting sheet by soldering (Fig. 9A, 150, [0080], [0083]), and
arranging the conductive cover plate comprises: arranging solder on the surface of the second bare die away from the first conductive frame, placing the flat plate of the conductive cover plate on the solder, and electrically connecting the conductive cover plate to the second bare die by soldering (153aF, [0081], [0083]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ohguro (U.S. PGPub 2022/0084917) in view of Ikeda (U.S. PGPub 2020/0273833).
Regarding claim 10, Ohguro does not explicitly teach wherein the conductive cover plate comprises three side plates vertically connected to the flat plate.
Ikeda teaches a chip package comprising a first conductive frame, a first bare die, a first conductive connecting sheet, a second bare die, and a conductive cover plate stacked and electrically connected (Fig. 17, 11, 13, 60, 21, 70, [0054]-[0058]), wherein the conductive cover plate comprises three side plates vertically connected to a flat plate and connected to the first conductive frame (Figs. 17-18, 75, [0128]-[0133]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Ikeda with Ohguro such that the conductive cover plate comprises three side plates vertically connected to the flat plate for the purpose of increasing heat dissipation (Ikeda, [0130]).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ohguro (U.S. PGPub 2022/0084917) in view of Lopez (U.S. PGPub 2014/0063744).
Regarding claim 12, Ohguro teaches wherein the chips are power semiconductors ([0003]), and the chip package module according to claim 1 (see rejection of claim 1) but does not explicitly teach a power module, comprising a circuit board and the chip package module located on the circuit board.
Lopez teaches a chip package comprising a first conductive frame, a first bare die, a first conductive connecting sheet, a second bare die, and a conductive cover plate stacked and electrically connected (110, 120, 140, 130, 150, [0027]-[0030]) wherein the chip package is mounted to a PCB to form a power module ([0008]-[0009]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lopez with Ohguro such that the device comprises a power module, comprising a circuit board and the chip package module located on the circuit board for the purpose of forming a power module having a smaller footprint (Lopez, [0008]-[0009]; Ohguro, [0087]).
Regarding claim 13, Ohguro teaches wherein the chips are power semiconductors ([0003]), and the chip package module according to claim 1 (see rejection of claim 1) but does not explicitly teach an electronic device, comprising a circuit board and the chip package module located on the circuit board.
Lopez teaches a chip package comprising a first conductive frame, a first bare die, a first conductive connecting sheet, a second bare die, and a conductive cover plate stacked and electrically connected (110, 120, 140, 130, 150, [0027]-[0030]) wherein the chip package is mounted to a PCB to form an electronic device ([0008]-[0009]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lopez with Ohguro such that the device comprises an electronic device, comprising a circuit board and the chip package module located on the circuit board for the purpose of forming an electronic device having a smaller footprint (Lopez, [0008]-[0009]; Ohguro, [0087]).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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