DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I claims 1-7 in the reply filed on 7/13/2026 is acknowledged.
Claim 8-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected groups II and III, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/13/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lai 20210126013.
a. As to claim 1Lai teaches A semiconductor device, comprising: a first channel structure extending in a first direction in a stack structure(figure 5a-b and 2a and figure 3a item 104 or item 104/116 on the left nearest to the center item 116); a conductive layer extending in a second direction perpendicular to the first direction and surrounding at least partial of the first channel structure (item 114 see figure 2C item WCG); a first isolation structure extending in the first direction and the second direction (item 116); and a second isolation structure extending in the first direction and the second direction item 116 on the left edge), wherein the first channel structure and the conductive layer are disposed between the first isolation structure and the second isolation structure (figure 2a item 114 and the channel 104 are between the center 116 and the left 116), and wherein a first distance between a center of the first channel structure and the first isolation structure is less than a second distance between the center of the first channel structure and the second isolation structure (see figure 2a).
PNG
media_image1.png
738
1140
media_image1.png
Greyscale
b. As to claim 2, Lai teaches wherein the first channel structure comprises: a semiconductor core extending in the first direction in the stack structure (alternative channel item 104); and a gate dielectric layer laterally surrounding the semiconductor core and extending in the first direction in the stack structure(items 110 and 112).
c. As to claim 3, Lai teaches wherein the gate dielectric layer is in contact with the first isolation structure (see figure 2 item 110 and 112 in contact with item 116).
d. As to claim 4, Lai teaches wherein the gate dielectric layer is in contact with the conductive layer (see figure items 112 and item 110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Chien 20230081427.
a. As to claim 5, Lai teaches paragraph 28:
With continued reference to FIGS. 1A-1C, the semiconductor channel 104 extends from the lower source/drain region 106l to the upper source/drain region 106u. The semiconductor channel 104 may, for example, be doped or undoped and may, for example, be or comprise polysilicon on and/or some other suitable semiconductor material(s). The semiconductor channel 104 may, for example, have a thickness (e.g., in an X direction) of about 10-30 nanometers, about 10-20 nanometers, about 20-30 nanometers, or some other suitable value.
Lai does not explicitly teach wherein the semiconductor core comprises indium gallium zinc oxide (IGZO).
Chien teaches forming the channels from oxide semiconductors (see abstract).
However, IZGO was known to be used for semiconductor channel for power efficiency and lower leakage.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the channel from IZGO for power efficiency and low leakage current.
Allowable Subject Matter
Claims 6-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Lai does not teach the feature of claim 6 or 7.
Lai 11171157 teaches 1a to 2a a similar structure with item 104 as a channel and item 106 as a dielectric. It is noted that a portion of item 104 would be between vertical 106s but 104 is a different channel thus it does not teach the feature of claim 6:
wherein the first channel structure comprises: a semiconductor core extending in the first direction in the stack structure; a first gate dielectric layer laterally surrounding a first portion of the semiconductor core; and a second gate dielectric layer laterally surrounding a second portion of the semiconductor core, wherein the first gate dielectric layer is separated from the second gate dielectric layer by a third portion of the semiconductor core between the first portion and the second portion since the first portion and second portion are different devices figure 3 in the vertical direction 203 is between 206a and 206b.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
Prosecution Insights