DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status
The instant Office Action is in response to applicant’s remarks filed on 08/07/2026. Claims 4-5 are canceled, and no new claims are appended. Claims 1-3 are pending, with claims 4-5 remaining cancelled.
Response to Arguments
Applicant's arguments filed on 08/07/2026 are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 & 3 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US Patent Application Publication 2012/0307410A1) in view of Seshita (US Patent Application Publication 2022/0302103A1).
Regarding claim 1, Yamazaki (US Patent Application Publication 2012/0307410A1) teaches An ESD protection circuit (ESD protective circuit 1, Figure 1, paragraph 0008, line 1), comprising: a protective element having a first node (protection MOS transistor 5, Figure 1, paragraph 0008 lines 3-5 + paragraph 0009 lines 1-5), placed between a power supply terminal (power supply terminal 2T + power supply line 2, Figure 1, paragraph 0061 line 2-4+ paragraph 0008 line 3-4) and a ground terminal (ground terminal 3T + ground line 3, Figure 1, paragraph 0061 line + paragraph 0008 line 3-5); an RC circuit (RC series circuit, Figure 1, paragraph 0009, lines 8-11) having a resistive element (resistive element R, Figure 1, paragraph 0009, line 8) connected to the power supply terminal at one end and a capacitive element (capacitive element C, Figure 1, paragraph 0009, line 9) connected to the ground terminal at one end and to the other end of the resistive element at the other end, the other ends of the resistive element and the capacitive element being a second node(potential VRC, Figure 1, paragraph 0012, lines 3-5); and an inverter (CMOS inverter 4, Figure 1, paragraph 0009, lines 11-14)connected to the second node of the RC circuit at its input and to the first node of the protective element at its output, wherein the inverter includes a p-type MOS transistor (PMOS transistor 4P, Figure 1, paragraph 0068) connected to the power supply terminal at its source, and an n-type MOS transistor (NMOS transistor 4N, Figure 1, paragraph 0068) connected to the ground terminal at its source, the p-type MOS transistor and the n-type MOS transistor are connected in common to the second node at their gates and to the first node at their drains (Figure 1, paragraph 0069, lines 4-6), as claimed.
Yamazaki (US Patent Application Publication 2012/0307410A1) is silent to teach a gate length of the p-type MOS transistor is smaller than a gate length of the n-type MOS transistor.
In an analogous art, Seshita (US Patent Application Publication 2022/0302103A1) teaches a gate length of the p-type MOS transistor (transistor PM1, Figure 2, paragraph 0040) is smaller (Figure 2, paragraph 0043) than a gate length of the n-type MOS transistor (transistor NM1, Figure 2, paragraph 0040), as claimed.
Therefore it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Yamazaki (US Patent Application Publication 2012/0307410A1) by varying the gate lengths of the p-type and n-type MOS transistors as taught by Seshita (US Patent Application Publication 2022/0302103A1) thereby having a smaller gate length for the p-type MOS transistor than the n-type MOS transistor.
Regarding claim 3, Yamazaki (US Patent Application Publication 2012/0307410A1) and Seshita (US Patent Application Publication 2022/0302103A1) teach the ESD protection circuit of claim 1, as claimed. Yamazaki (US Patent Application Publication 2012/0307410A1) further teaches wherein the protective element is a second n-type MOS transistor (protection MOS transistor 5, Figure 1, paragraph 0065, lines 1-3) connected to the first node at its gate, to the ground terminal at its source (Figure 1, paragraph 0065, lines 3-4), and to the power supply terminal at its drain (Figure 1, paragraph 0065, lines 4).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US Patent Application Publication 2012/0307410A1) and Seshita (US Patent Application Publication 2022/0302103A1) in view of Masuoka (US Patent Application Publication 2006/0145265A1).
Regarding claim 2, Yamazaki (US Patent Application Publication 2012/0307410A1) and Seshita (US Patent Application Publication 2022/0302103A1) teach the ESD protection circuit of claim 1, as claimed.
Yamazaki (US Patent Application Publication 2012/0307410A1) and Seshita (US Patent Application Publication 2022/0302103A1) are silent to teach wherein a thickness of a gate insulating film of the n-type MOS transistor is larger than a thickness of a gate insulating film of the p-type MOS transistor.
In an analogous art, Masuoka (US Patent Application Publication 2006/0145265A1) teaches wherein a thickness of a gate insulating film of the n-type MOS transistor (gate insulating film 106a) is larger (Figure 1, paragraph 0033) than a thickness of a gate insulating film of the p-type MOS transistor (gate insulating film 106b), as claimed.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings of Yamazaki (US Patent Application Publication 2012/0307410A1) and Seshita (US Patent Application Publication 2022/0302103A1) by varying the gate insulating film thickness of the p-type and n-type MOS transistors as taught by Masuoka (US Patent Application Publication 2006/0145265A1) thereby having a smaller gate insulating film thickness for the p-type MOS transistor than the n-type MOS transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
