DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on June 24, 2026.
Claims 1-4, 6, 9-12, 14, 17-21 and 23-27 are pending. Claims 1, 9 and 17 are amended. Claims 5, 7-8, 13, 15-16 and 22 are canceled. Claims 23-27 are newly added. Claims 1, 9 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 24, 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 9-12, 14, 17, 19-21, 23, 25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20160343444) in view of Chai et al. (US 20250131962).
Regarding independent claim 1, Park et al. disclose a method of operating a memory device comprising at least a block of memory cells [see Fig. 3, a method in which the nonvolatile memory device 110 performs an erase operation with respect to a selected erase unit (e.g., memory block or sub block), para. 75], the method comprising:
applying a first set of erase pulses to erase the block of memory cells in a first set of erase cycles, respectively, wherein the first set of erase pulses comprises one or more first erase voltages having varied voltage values [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97]; and
responsive to detecting that the block of memory cells has not been successfully erased [see Fig. 3: S130, the loop is repeated until the pass/fail check circuit PF performs a pass check, para. 84] and that an erase cycle count reaches a cycle threshold [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected. If during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], applying a second set of erase pulses to erase the block of memory cells in a second set of erase cycles, respectively, wherein the second set of erase pulses comprises one or more second erase voltages each of which has a respective voltage value smaller than a voltage value of one of the one or more first erase voltages [see Fig. 4 and 18 with respect to Fig. 3: step S110-S160, the voltage control circuit VC decreases a level of the erase voltage VERS, para. 88-89 as well as para. 96],
wherein an increment step pulse erase (ISPE) scheme is applied to erase the block of memory cells [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97];
the one or more first erase voltages comprise one or more increment step pulses [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97], and
the one or more second erase voltages comprise one or more pulses having an identical voltage value [see Fig. 4 with respect to Fig. 3: step S110-S160, the voltage control circuit VC decreases a level of the erase voltage VERS, para. 88-89 as well as para. 96. An erase loop is repeated after a decrease of the erase voltage VERS is decided, a level of the erase voltage VERS may continuously decrease or may maintain a specific value after it is decreased by the predetermined number of times, para. 108],
wherein responsive to detecting that the block of memory cells has not been successfully erased [see Fig. 3: S130, the loop is repeated until the pass/fail check circuit PF performs a pass check, para. 84] and that an erase cycle count reaches a cycle threshold [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected. If during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], applying the second set of erase pulses to erase the block of memory cells in the respective second set of erase cycles comprises:
in each of the second set of erase cycles, responsive to the erase cycle count being equal to or greater than the cycle threshold, applying a corresponding second erase voltage to erase the block of memory cells [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], and applying a verify voltage to verify the erasing of the block of memory cells [see Fig. 4 and 18, in a fourth erase loop EL4 (or the fifth erase loop EL5), the erase voltage VERS and the erase verification voltage VER are applied to memory cells MC of the selected erase unit, para. 96 as well as 188].
However, Park et al. are silent with respect to responsive to the erase cycle count being smaller than a maximum cycle count, applying a corresponding second erase voltage to erase the block of memory cells and responsive to the erase cycle count reaching the maximum cycle count, terminating the erasing of the block of memory cells.
Chai et al. teach responsive to the erase cycle count being smaller than a maximum cycle count, applying a corresponding second erase voltage to erase the block of memory cells [see Fig. 6: S60, when the count value of the current erase loop is not the maximum count value of the erase loop in S60 (NO in S60), S20 to S60 for the current erase loop, for example, the second erase loop EL2 may be sequentially performed, para. 148] and responsive to the erase cycle count reaching the maximum cycle count, terminating the erasing of the block of memory cells [see Fig. 6: S60, when the count value of the current erase loop is the maximum count value of the erase loop in S60 (YES in S60), the erase operation for the erase selection block may be determined to be a fail, and the erase operation may be then terminated, para. 147].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chai et al. to the teaching of Park et al. such that incorporating the maximum count value condition of Chai et al. into the erase loop method of Park et al. to prevent an erase loop from being infinitely repeated, reduce over-erase risk and improve erase operation efficiency.
Regarding claim 2, Park et al. in combination with Chai et al. teach the limitations with respect to claim 1.
Furthermore, Park et al. disclose wherein the cycle threshold is in a range between 3 and 6 [see Fig. 18, when the fourth erase loop EL4 is performed after the third erase loop EL3 is performed, the erase voltage VERS decreases by a first decrement DEC1, para. 190. That means after three erase loops, the erase voltage VERS starts decrease].
Regarding claim 3, Park et al. in combination with Chai et al. teach the limitations with respect to claim 1.
Furthermore, Park et al. disclose wherein the respective voltage value of each of the one or more second erase voltages is identical [an erase loop is repeated after a decrease of the erase voltage VERS is decided, a level of the erase voltage VERS may continuously decrease or may maintain a specific value after it is decreased by the predetermined number of times, para. 108].
Regarding claim 4, Park et al. in combination with Chai et al. teach the limitations with respect to claim 1.
Furthermore, Park et al. disclose wherein applying the first set of erase pulses to erase the block of memory cells in the first set of erase cycles, respectively, comprises:
in each of the first set of erase cycles [see Fig. 4 with respect to Fig. 3 step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97],
responsive to the erase cycle count being smaller than the cycle threshold, applying a corresponding first erase voltage to erase the block of memory cells [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected, para. 110]; and
applying a verify voltage to verify the erasing of the block of memory cells [see Fig. 4 with respect to Fig. 3: step S120, performing erase verification VER on memory cells MC to which the erase voltage VERS is applied, para. 78 as well as para. 93-95].
Regarding claim 6, Park et al. in combination with Chai et al. teach the limitations with respect to claim 4.
Furthermore, Park et al. disclose further comprising:
updating the erase cycle count that indicates a total number of erase cycles already performed to erase the block of memory cells [Park et al. disclose the pass/fail check circuit PF includes a counter CNT. The counter CNT can count the number of pass cells distinguished as an erase pass or the number of fail cells distinguished as an erase fail among data received from the page buffer circuit 115, para. 48. Park et al. also disclose the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed, para. 110. Therefore, it would have been obvious for a person having ordinary skill in the art to implement the counter CNT to count the number of times an erase loop is performed].
Regarding independent claim 9, Park et al. disclose a memory device [see Fig. 1: 110, para. 37], comprising:
a block of memory cells [see Fig. 2, para. 50]; and
a peripheral circuit coupled to the block of memory cells [Fig 1: 119, para. 41-44] and configured to:
apply a first set of erase pulses to erase the block of memory cells in a first set of erase cycles, respectively, wherein the first set of erase pulses comprises one or more first erase voltages having varied voltage values [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97]; and
responsive to detecting that the block of memory cells has not been successfully erased [see Fig. 3: S130, the loop is repeated until the pass/fail check circuit PF performs a pass check, para. 84] and that an erase cycle count reaches a cycle threshold [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected. If during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], apply a second set of erase pulses to erase the block of memory cells in a second set of erase cycles, respectively, wherein the second set of erase pulses comprises one or more second erase voltages each of which has a respective voltage value smaller than a voltage value of one of the one or more first erase voltages [see Fig. 4 with respect to Fig. 3: step S110-S160, the voltage control circuit VC decreases a level of the erase voltage VERS, para. 88-89 as well as para. 96],
wherein an increment step pulse erase (ISPE) scheme is applied to erase the block of memory cells [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97];
the one or more first erase voltages comprise one or more increment step pulses [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97], and
the one or more second erase voltages comprise one or more pulses having an identical voltage value [see Fig. 4 with respect to Fig. 3: step S110-S160, the voltage control circuit VC decreases a level of the erase voltage VERS, para. 88-89 as well as para. 96. An erase loop is repeated after a decrease of the erase voltage VERS is decided, a level of the erase voltage VERS may continuously decrease or may maintain a specific value after it is decreased by the predetermined number of times, para. 108],
wherein responsive to detecting that the block of memory cells has not been successfully erased [see Fig. 3: S130, the loop is repeated until the pass/fail check circuit PF performs a pass check, para. 84] and that an erase cycle count reaches a cycle threshold [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected. If during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], applying the second set of erase pulses to erase the block of memory cells in the respective second set of erase cycles comprises:
in each of the second set of erase cycles, responsive to the erase cycle count being equal to or greater than the cycle threshold, applying a corresponding second erase voltage to erase the block of memory cells [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], and applying a verify voltage to verify the erasing of the block of memory cells [see Fig. 4 and 18, in a fourth erase loop EL4 (or the fifth erase loop EL5), the erase voltage VERS and the erase verification voltage VER are applied to memory cells MC of the selected erase unit, para. 96 as well as 188].
However, Park et al are silent with respect to responsive to the erase cycle count being smaller than a maximum cycle count, applying a corresponding second erase voltage to erase the block of memory cells and responsive to the erase cycle count reaching the maximum cycle count, terminating the erasing of the block of memory cells.
Chai et al. teach responsive to the erase cycle count being smaller than a maximum cycle count, applying a corresponding second erase voltage to erase the block of memory cells [see Fig. 6: S60, when the count value of the current erase loop is not the maximum count value of the erase loop in S60 (NO in S60), S20 to S60 for the current erase loop, for example, the second erase loop EL2 may be sequentially performed, para. 148] and responsive to the erase cycle count reaching the maximum cycle count, terminating the erasing of the block of memory cells [see Fig. 6: S60, when the count value of the current erase loop is the maximum count value of the erase loop in S60 (YES in S60), the erase operation for the erase selection block may be determined to be a fail, and the erase operation may be then terminated, para. 147].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chai et al. to the teaching of Park et al. such that incorporating the maximum count value condition of Chai et al. into the erase loop method of Park et al. to prevent an erase loop from being infinitely repeated, reduce over-erase risk and improve erase operation efficiency.
Regarding claim 10, Park et al. in combination with Chai et al. teach the limitations with respect to claim 9.
Furthermore, Park et al. disclose wherein the cycle threshold is in a range between 3 and 6 [see Fig. 18, when the fourth erase loop EL4 is performed after the third erase loop EL3 is performed, the erase voltage VERS decreases by a first decrement DEC1, para. 190. That means after three erase loops, the erase voltage VERS starts decrease].
Regarding claim 11, Park et al. in combination with Chai et al. teach the limitations with respect to claim 9.
Furthermore, Park et al. disclose wherein the respective voltage value of each of the one or more second erase voltages is identical [an erase loop is repeated after a decrease of the erase voltage VERS is decided, a level of the erase voltage VERS may continuously decrease or may maintain a specific value after it is decreased by the predetermined number of times, para. 108].
Regarding claim 12, Park et al. in combination with Chai et al. teach the limitations with respect to claim 9.
Furthermore, Park et al. disclose wherein to apply the first set of erase pulses to erase the block of memory cells in the first set of erase cycles, respectively, the peripheral circuit is further configured to:
in each of the first set of erase cycles [see Fig. 4 with respect to Fig. 3 step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97],
responsive to the erase cycle count being smaller than the cycle threshold, applying a corresponding first erase voltage to erase the block of memory cells [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected, para. 110]; and
apply a verify voltage to verify the erasing of the block of memory cells [see Fig. 4 with respect to Fig. 3: step S120, performing erase verification VER on memory cells MC to which the erase voltage VERS is applied, para. 78 as well as para. 93-95].
Regarding claim 14, Park et al. in combination with Chai et al. teach the limitations with respect to claim 12.
Furthermore, Park et al. disclose the peripheral circuit is further configured to:
update the erase cycle count that indicates a total number of erase cycles already performed to erase the block of memory cells [Park et al. disclose the pass/fail check circuit PF includes a counter CNT. The counter CNT can count the number of pass cells distinguished as an erase pass or the number of fail cells distinguished as an erase fail among data received from the page buffer circuit 115, para. 48. Park et al. also disclose the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed, para. 110. Therefore, it would have been obvious for a person having ordinary skill in the art to implement the counter CNT to count the number of times an erase loop is performed].
Regarding independent claim 17, Park et al. disclose a system [see Fig. 21: 100, para. 216], comprising:
a memory device [Figs. 21: 110 with respect to Fig. 1: 110] configured to store data [para. 42 as well as para. 213] and comprising:
a block of memory cells [see Fig. 2, para. 50]; and
a peripheral circuit coupled to the block of memory cells [Fig 1: 119, para. 41-44] and configured to perform operations comprising:
apply a first set of erase pulses to erase the block of memory cells in a first set of erase cycles, respectively, wherein the first set of erase pulses comprises one or more first erase voltages having varied voltage values [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97]; and
responsive to detecting that the block of memory cells has not been successfully erased [see Fig. 3: S130, the loop is repeated until the pass/fail check circuit PF performs a pass check, para. 84] and that an erase cycle count reaches a cycle threshold [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected. If during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], apply a second set of erase pulses to erase the block of memory cells in a second set of erase cycles, respectively, wherein the second set of erase pulses comprises one or more second erase voltages each of which has a respective voltage value smaller than a voltage value of one of the one or more first erase voltages [see Fig. 4 with respect to Fig. 3: step S110-S160, the voltage control circuit VC decreases a level of the erase voltage VERS, para. 88-89 as well as para. 96],
wherein an increment step pulse erase (ISPE) scheme is applied to erase the block of memory cells [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97];
the one or more first erase voltages comprise one or more increment step pulses [see Fig. 4 with respect to Fig. 3: step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97], and
the one or more second erase voltages comprise one or more pulses having an identical voltage value [see Fig. 4 with respect to Fig. 3: step S110-S160, the voltage control circuit VC decreases a level of the erase voltage VERS, para. 88-89 as well as para. 96. An erase loop is repeated after a decrease of the erase voltage VERS is decided, a level of the erase voltage VERS may continuously decrease or may maintain a specific value after it is decreased by the predetermined number of times, para. 108],
wherein responsive to detecting that the block of memory cells has not been successfully erased [see Fig. 3: S130, the loop is repeated until the pass/fail check circuit PF performs a pass check, para. 84] and that an erase cycle count reaches a cycle threshold [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected. If during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], applying the second set of erase pulses to erase the block of memory cells in the respective second set of erase cycles comprises:
in each of the second set of erase cycles, responsive to the erase cycle count being equal to or greater than the cycle threshold, applying a corresponding second erase voltage to erase the block of memory cells [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is greater than the critical value, a decrease of the erase voltage VERS may be selected, para. 110], and applying a verify voltage to verify the erasing of the block of memory cells [see Fig. 4 and 18, in a fourth erase loop EL4 (or the fifth erase loop EL5), the erase voltage VERS and the erase verification voltage VER are applied to memory cells MC of the selected erase unit, para. 96 as well as 188]; and
a memory controller [Fig. 21: 120] coupled to the memory device and configured to control the memory device to perform the operations [para. 211].
However, Park et al are silent with respect to responsive to the erase cycle count being smaller than a maximum cycle count, applying a corresponding second erase voltage to erase the block of memory cells and responsive to the erase cycle count reaching the maximum cycle count, terminating the erasing of the block of memory cells.
Chai et al. teach responsive to the erase cycle count being smaller than a maximum cycle count, applying a corresponding second erase voltage to erase the block of memory cells [see Fig. 6: S60, when the count value of the current erase loop is not the maximum count value of the erase loop in S60 (NO in S60), S20 to S60 for the current erase loop, for example, the second erase loop EL2 may be sequentially performed, para. 148] and responsive to the erase cycle count reaching the maximum cycle count, terminating the erasing of the block of memory cells [see Fig. 6: S60, when the count value of the current erase loop is the maximum count value of the erase loop in S60 (YES in S60), the erase operation for the erase selection block may be determined to be a fail, and the erase operation may be then terminated, para. 147].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Chai et al. to the teaching of Park et al. such that incorporating the maximum count value condition of Chai et al. into the erase loop method of Park et al. to prevent an erase loop from being infinitely repeated, reduce over-erase risk and improve erase operation efficiency.
Regarding claim 19, Park et al. in combination with Chai et al. teach the limitations with respect to claim 17.
Furthermore, Park et al. disclose wherein the respective voltage value of each of the one or more second erase voltages is identical [an erase loop is repeated after a decrease of the erase voltage VERS is decided, a level of the erase voltage VERS may continuously decrease or may maintain a specific value after it is decreased by the predetermined number of times, para. 108].
Regarding claim 20, Park et al. in combination with Chai et al. teach the limitations with respect to claim 17.
Furthermore, Park et al. disclose wherein to apply the first set of erase pulses to erase the block of memory cells in the first set of erase cycles, respectively, the peripheral circuit is further configured to:
in each of the first set of erase cycles [see Fig. 4 with respect to Fig. 3 step S110-S150, the control logic circuit 119 can increase the erase voltage VERS in early erase loops of an erase operation (erase loops EL1-EL3), para. 88-89 as well as para. 93-97],
responsive to the erase cycle count being smaller than the cycle threshold, applying a corresponding first erase voltage to erase the block of memory cells [the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed. For example, if during one erase operation, the number of times an erase loop is performed is smaller than a critical value, an increase of the erase voltage VERS may be selected, para. 110]; and
apply a verify voltage to verify the erasing of the block of memory cells [see Fig. 4 with respect to Fig. 3: step S120, performing erase verification VER on memory cells MC to which the erase voltage VERS is applied, para. 78 as well as para. 93-95].
Regarding claim 21, Park et al. in combination with Chai et al. teach the limitations with respect to claim 17.
Furthermore, Park et al. disclose the peripheral circuit is further configured to:
update the erase cycle count that indicates a total number of erase cycles already performed to erase the block of memory cells [Park et al. disclose the pass/fail check circuit PF includes a counter CNT. The counter CNT can count the number of pass cells distinguished as an erase pass or the number of fail cells distinguished as an erase fail among data received from the page buffer circuit 115, para. 48. Park et al. also disclose the control method of the erase voltage VERS may be decided according to the number of times an erase loop is performed, para. 110. Therefore, it would have been obvious for a person having ordinary skill in the art to implement the counter CNT to count the number of times an erase loop is performed].
Regarding claim 23, Park et al. in combination with Chai et al. teach the limitations with respect to claim 1.
Furthermore, Chai et al. disclose further comprising:
responsive to terminating the erasing of the block of memory cells, marking the block of memory cells as a malfunctioning block that cannot be reused [see Fig. 6: S60, when the count value of the current erase loop is the maximum count value of the erase loop in S60 (YES in S60), the erase operation for the erase selection block may be determined to be a fail, and the erase operation may be then terminated, para. 147. It would have been obvious to mark the block as a malfunctioning block that cannot be reused after failed termination, because a block that cannot be successfully erased cannot reliably store new data, and preventing further use of that block would predictably improve memory reliability and avoid future program errors].
Regarding claim 25, Park et al. in combination with Chai et al. teach the limitations with respect to claim 9.
Furthermore, Chai et al. disclose the peripheral circuit is further configured to:
responsive to terminating the erasing of the block of memory cells, mark the block of memory cells as a malfunctioning block that cannot be reused [see Fig. 6: S60, when the count value of the current erase loop is the maximum count value of the erase loop in S60 (YES in S60), the erase operation for the erase selection block may be determined to be a fail, and the erase operation may be then terminated, para. 147. It would have been obvious to mark the block as a malfunctioning block that cannot be reused after failed termination, because a block that cannot be successfully erased cannot reliably store new data, and preventing further use of that block would predictably improve memory reliability and avoid future program errors].
Regarding claim 27, Park et al. in combination with Chai et al. teach the limitations with respect to claim 17.
Furthermore, Chai et al. disclose wherein the peripheral circuit is further configured to:
responsive to terminating the erasing of the block of memory cells, mark the block of memory cells as a malfunctioning block that cannot be reused [see Fig. 6: S60, when the count value of the current erase loop is the maximum count value of the erase loop in S60 (YES in S60), the erase operation for the erase selection block may be determined to be a fail, and the erase operation may be then terminated, para. 147. It would have been obvious to mark the block as a malfunctioning block that cannot be reused after failed termination, because a block that cannot be successfully erased cannot reliably store new data, and preventing further use of that block would predictably improve memory reliability and avoid future program errors].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20160343444) in view of Chai et al. (US 20250131962) as applied to claim 17 above, and further in view of Jessani et al. (US 20070198787).
Regarding claim 18, Park et al. in combination with Chai et al. teach the limitations with respect to claim 17.
However, Park et al. in combination with Chai et al. are silent with respect to disclose wherein:
the peripheral circuit comprises at least one processor, a read-only memory (ROM) storing first instructions, and a random-access memory (RAM) storing second instructions;
the first instructions comprise a first instruction segment, a second instruction segment, and a third instruction segment, wherein the second instructions stored in the RAM are configured to replace the second instruction segment stored in the ROM; and
the at least one processor is configured to perform the operations by executing the first instruction segment stored in the ROM, the second instructions stored in the RAM, and the third instruction segment stored in the ROM.
Jessani et al. teach the peripheral circuit comprises at least one processor [Fig. 2: 136], a read-only memory (ROM) [Fig. 2: 138] storing first instructions, and a random-access memory (RAM) [Fig. 2: 140] storing second instructions [para. 24-25];
the first instructions comprise a first instruction segment [see Fig. 5, address X 502 and the address X2 506, para. 45], a second instruction segment [address 512a…c], and a third instruction segment [address RTN_ADDR_0], wherein the second instructions stored in the RAM are configured to replace the second instruction segment stored in the ROM [para. 45]; and
the at least one processor is configured to perform the operations by executing the first instruction segment stored in the ROM [Fig. 6: step 702], the second instructions stored in the RAM [Fig. 6: step 706], and the third instruction segment stored in the ROM [Fig. 6: step 722, para. 11-13 as well as para. 46-48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Jessani et al. to the teaching of Park et al. in combination with Chai et al. such that patching ROM code by jumping to RAM at reserved ROM addresses and then returning to ROM as taught by Jessani et al. to the peripheral circuit as taught by Park et al. in combination with Chai et al. to achieve a scalable, low-overhead patch mechanism using only two comparators for an unlimited number of patch memory blocks instead of a comparator for each patch memory block [see Jessani et al.’s para. 45].
Claims 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20160343444) in view of Chai et al. (US 20250131962) as applied to claims 1 and 9 above, and further in view of Kim et al. (US 20170062059).
Regarding claims 24 and 26, Park et al. in combination with Chai et al. teach the limitations with respect to claims 1 and 9, respectively.
Furthermore, Chai et al. disclose further comprising: before applying the first set of erase pulses, initializing the erase cycle count to 0 [Chai et al. use a current erase loop count that is increased after erase failure and compared with a maximum count, para. 145-148. A person of ordinary in the art would normally initialize that count before the first erase loop so that the count accurately reflects loops performed from the beginning].
However, Park et al. in combination with Chai et al. are silent with respect to before applying the first set of erase pulses, pre-programming the block of memory cells.
Kim et al. teach before applying the first set of erase pulses, pre-programming the block of memory cells [the pre-program controller 121 is configured to generate the pre-programming control signal to cause the pre-program operation to be performed before the erase operation is performed on the memory cell array 110, para. 69].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Kim et al. to the teaching of Park et al. in combination with Chai et al. such that pre-programming the block of memory cells before applying the first set of erase pulses as taught by Kim et al. in the erase operation of Park et al. in combination with Chai et al. to reduce over-erasure [see Kim et al.’s para. 101].
Response to Arguments
Applicant's arguments filed on June 24, 2026 with respect to claim 1 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserts that “Chai’s maximum-count check is disclosed in the context of Chai’s increasing-voltage ISPE erase-loop process”, and that “Office Action does not provide a rational basis for specifically applying Chai’s maximum-count check to Park’s post-threshold decreased-voltage erase loops”. Applicant further agues that “Park's post-threshold erase loops deliberately reduce or maintain the erase voltage to avoid deep erase and cell stress”, whereas Chai’s erase operation increases erase voltage according to ISPE method. Thus, Applicant asserts that “neither Park nor Chai provides a rational basis for applying such a maximum-count check, disclosed for terminating an increasing-voltage ISPE erase-loop process, specifically to opposite, decreased-voltage erase loops in Park”, see Applicant’s Remarks pages 9-11. This particular remark is not considered persuasive.
The rejection does not rely on Chai for the post threshold decreased or maintain erase voltage profile. Rather, Park is relied upon for the erase voltage control profile, including increasing erase voltage in early erase loops and decreasing or maintaining the erase voltage in later erase loops. Park also teaches after a decrease of the erase voltage VERS is decided, a level of the erase voltage VERS may continuously decrease or may maintain a specific value after it is decreased by the predetermined number of times [para. 108]. Accordingly, Park teaches or suggests the claimed “second erase voltages” having an identical voltage value because Park’s later erase loops may apply a decreasing erase voltage and then maintain that decreased value across repeated erase loops. The maintained decreased VERS corresponds to the claimed second erase voltages having an identical voltage value, and that decreased value is smaller than the voltage value of a prior first erase voltage.
Chai is relied upon for the known erase loop control feature of checking a maximum erase loop count after an unsuccessful erase verification and terminating the erase operation when the maximum count is reached. Although Chai describes ISPE as increasing erase voltage step by step, Applicant’s argument improperly limits Chai’s maximum count termination feature to only increasing voltage erase loops. Chai’s maximum count check is a general loop-control and fail-termination mechanism used after erase verification failure. The function of that mechanism is to prevent indefinite repetition of erase loops and to declare failure when the erase voltage has not succeeded after a maximum number of attempts. That function is independent of whether the erase voltage in a particular loop is increased, decreased, or maintained.
The proposed combination therefore does not incorporate Chai’s increasing voltage profile into Park’s late erase loops. Rather, the combined method uses Park’s erase voltage control profile and Chai’s known maximum-count termination logic. In the combined method, Park’s early erase loops apply increasing erase voltages; after the erase cycle count reaches Park’s critical value and the block has not been successfully erased, Park’s later erase loops apply a decreased and maintained erase voltage. Chai’s maximum-count check is then applied to the repeated erase loop process so that the controller continues the later erase loops while the erase cycle count is less than the maximum count and terminates the erase operation when the maximum count is reached.
This modification is consistent with, rather than contrary to, Park’s stated purpose. Park seeks to avoid deep erase and cell stress caused by repeated increasing the erase voltage. Applying Chai’s maximum-count check termination to Park’s later erase loops would further limit unnecessary erase attempts and thereby further reduce stress and unnecessary erase time. Thus, Park does not teach away from the proposed combination.
A person of ordinary skill in the art would have been motivated to apply Chai’s maximum-count termination to Park’s repeated erase loop process because both Chai and Park are directed to controlling erase operations in nonvolatile memory devices using repeated erase loops and verification. Chai’s maximum-count check would have predictably provided a known benefit: terminating an erase operation as failed when repeated erase attempts do not successfully erase the selected block. The modification would have required only routine control logic implementation and would have produced the predictable result of preventing endless erase loop repetition.
For the above reasons, the applied rejection is considered proper and maintained. The independent claims 9 and 17 were argued for substantially the same reason, and the arguments are not persuasive for the same reason.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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