Notice of Pre-AIA or AIA Status
This application, 18/671501, attorney docket 10018-01-0559-US, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The applicant or assignee is Yangtze Memory Technologies Co., Ltd.., and is a Continuation of PCT/CN2024/084125, filed 03/27/2024. Applicant’s election without traverse of inventive group I, claims 1-11 in the reply filed on 8/25/2026 is acknowledged. Claims 12-20 are withdrawn. Examiner notes request for rejoinder. Claims 1-11 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Claim 5 recites, “the semiconductor device of claim 1, wherein the contact structure further comprises a second end away from the semiconductor structure, and a first width of the first end in the third direction is greater than a second width of the second end in the third direction,” but the drawings do not show a contact with varied widths. Therefore, the contact with varied width must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “a first gate structure and a second gate structure extending in a first direction and a second direction perpendicular to the first direction.” It is not clear if both gate extend in 2 direction or if they extend perpendicular to each other. Neither interpretation is supported by the disclosure because all of the figures show the gates extending in the same direction with a width in a perpendicular direction, so examiner will interpret the claim in view of the drawings.
Dependent claims include the defect of the parent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Kim et al. (U.S. 2018/0358450)
As for claim 1,
Kim teaches in figure 2 a semiconductor device, comprising:
a first gate structure (151) and a second gate structure (152) extending in a first direction and a second direction perpendicular to the first direction (Y and Z);
a first isolation structure (140) deposited between the first gate structure and the second gate structure extending in the first direction and the second direction;
a first semiconductor structure (123) deposited between the first gate structure and the first isolation structure extending in the first direction;
a first contact structure (163) deposited on the first semiconductor structure;
a first dielectric layer (132) deposited on the first gate structure;
and a second dielectric layer (171) deposited on the first isolation structure,
wherein the first contact structure comprises a first end in contact with the first semiconductor structure, a first center of the first end of the first contact structure in a third direction perpendicular to the first direction and the second direction aligns with a second center of the first semiconductor structure in the third direction. (centers are aligned in the X direction in figure 2).
As for claim 3,
Kim teaches the semiconductor device of claim 1, wherein the first isolation structure comprises an isolation core (117) and a third dielectric layer (173) between the isolation core and the first semiconductor structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chu et al. (U.S. 10,903,143).
As for claim 2,
Kim teaches the semiconductor device of claim 1, but does not teach that the first center aligns with the second center in the first direction,
However, Chu teaches in figure 1, the contact GC1 centered on the source GS1 in the X and Y direction.
It would have been obvious to one skilled in the art at the effective filing date of this application center the contact to maximize the contact area with a minimal footprint without the contact landing outside the contact point and causing possible shorts. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Shue et al. (U.S. 2013/0320459).
As for claim 4,
Kim teaches the semiconductor device of claim 1, but does not teach that the first isolation structure comprises an air gap extending in the first direction.
However, Shue teaches using an air gap (154) in the isolation in figure 4.
It would have been obvious to one skilled in the art at the effective filing date of this application toad the air gap of Shue to the device of Kim to reduce leakage current between devices. Shue [0025]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 6,
Kim teaches the semiconductor device of claim 1, but is silent on a second isolation structure
a second isolation structure, the first gate structure located between the first isolation structure and the second isolation structure;
a second semiconductor structure deposited between the first gate structure and the second isolation structure;
and a second contact structure deposited on the second semiconductor structure, wherein each of the first contact structure and the second contact structure comprises a first inner edge close to the first gate structure and a first outer edge away from the first gate structure, each of the first isolation structure and the second isolation structure comprises a second inner edge close to the first gate structure and a second outer edge away from the first gate structure; and a third center between the first outer edge of the first contact structure and the first outer edge of the second contact structure in the third direction aligns with a fourth center between the second inner edge of the first isolation structure and the second inner edge of the second isolation structure in the third direction.
However Shue teaches a second isolation on the opposing side of the gate in figure 4.
The court has held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. In re Harza establishes "a mere duplication of parts has no patentable significance unless a new and unexpected result is produced." 274 F.2d 669, 124 USPQ 378 (CCPA 1960); See, MPEP 2144.04 (VI)(C). Here, the applicant has not disclosed any unexpected results, and the additional isolation regions merely expand the capacity of the device. Therefore, it would have been obvious to one skilled in the art at the invention was made to add the additional isolation regions that are the same as 140 of Kim on the other sides of the gates.
As for claim 7,
Kim in view of Shue makes obvious the semiconductor device of claim 6, and in the combination, which uses the contacts of Kim, the third center align with the fourth center along the first direction as shown in figure 4.
As for claim 8.
Kim teaches a semiconductor device, comprising:
a first isolation structure (140) and a second isolation structure extending in a first direction and a second direction perpendicular to the first direction;
a gate structure (151) deposited between the first isolation structure and the second isolation structure (would be the same as the first, see below) extending in the first direction and the second direction;
a first semiconductor structure (123) deposited between the gate structure and the first isolation structure extending in the first direction;
a second semiconductor structure (123, on the opposng side of the gate) deposited between the gate structure and the second isolation structure extending in the first direction;
a first contact structure (163) deposited on the first semiconductor structure, the first contact structure comprising a first inner edge close to the gate structure and a first outer edge away from the gate structure; and
a second contact structure (163) deposited on the second semiconductor structure, the second contact structure comprising a second inner edge close to the gate structure and a second outer edge away from the gate structure,
wherein the first isolation structure comprises a first isolation core (142) and a first dielectric layer (141) between the first isolation core and the first semiconductor structure, the second isolation structure comprises a second isolation core and a second dielectric layer between the second isolation core and the second semiconductor structure (would be the same as the first isolation, see below); and
a first distance between the first outer edge of the first contact structure and an edge of the first dielectric layer in a third direction perpendicular to the first direction and the second direction is equal to a second distance between the second outer edge of the second contact structure and an edge of the second dielectric layer in the third direction (shown in figure 2).
Kim does not teach a second isolation structure.
However, Shue teaches a second isolation on the opposing side of the gate in figure 4.
The court has held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. In re Harza establishes "a mere duplication of parts has no patentable significance unless a new and unexpected result is produced." 274 F.2d 669, 124 USPQ 378 (CCPA 1960); See, MPEP 2144.04 (VI)(C). Here, the applicant has not disclosed any unexpected results, and the additional isolation regions merely expand the capacity of the device. Therefore, it would have been obvious to one skilled in the art at the invention was made to add the additional isolation regions that are the same as 140 of Kim on the other sides of the gates.
As for claim 9,
Kim in view of Shue makes obvious the semiconductor device of claim 8, and in the combination, Shue teaches each of the first isolation structure and the second isolation structure comprises an air gap extending in the first direction.
It would have been obvious to one skilled in the art at the effective filing date of this application toad the air gap of Shue to the device of Kim to reduce leakage current between devices. Shue [0025]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 10,
Kim in view of Shue makes obvious the semiconductor device of claim 8, and in the combination, Kim teaches
a second dielectric layer (132) deposited on the gate structure; and
a third dielectric layer (171) deposited on the first isolation structure, wherein a width of the second dielectric layer in the third direction is different from a width of the third dielectric layer in the third direction. (the dielectric above the gate extends to the contact, but the dielectric of the isolation stops short of the contact on both sides).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ting et al. (U.S. 2016/0155739).
As for claim 5,
Kim teaches the semiconductor device of claim 1, wherein the contact structure further comprises a second end away from the semiconductor structure, but does not teach that a first width of the first end in the third direction is greater than a second width of the second end in the third direction.
However, Ting teaches in figure 2B a contact with an upper width greater than a lower width.
It would have been obvious to one skilled in the art at the effective filing date of this application to form a tapered contact taught by Ting in the device of Kim because it allows the use of a anisotropic etch, or a self-aligned contact after forming a tapered gate sidewall. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Shue and in further view of Moon et al. (U.S. 2017/0018552).
As for claim 11,
Kim in view of Shue makes obvious the semiconductor device of claim 8, but the combination does not teach a storage structure coupled with the semiconductor structure through the contact structure.
However, Moon teaches in figure 8A, a storage structure (181/182/180) coupled with the semiconductor structure (SD) through the contact structure (BC).
It would have been obvious to one skilled in the art at the effective filing date of this application to add the storage structure to the device of Kim so that the transistor can be used as 1t-1c dram device.. One skilled in the art would have combined these elements with a reasonable expectation of success.
Conclusion
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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