Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based upon an application filed in KOREA on 08/16/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 5-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US20100025847A1; Tomura et al.; (hereinafter “Tomura”) in view of US20210020555A1; Herald et al.; (hereinafter “Herald”).
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Regarding Claim 1, Tomura teaches a semiconductor package ([0064]), comprising:
a substrate (#4, Figure 21 of Tomura annotated) defining a first trench structure (#T1) and a second trench structure (#T2) in an upper surface of the substrate (#4);
a semiconductor chip (#2) disposed on the substrate (#4); and
an underfill (#7) filling a space between the substrate (#4) and the semiconductor chip (#2),
the first trench structure (#T1) and the second trench structure (#T2) surrounding the semiconductor chip (#2),
the first trench structure (#T1) including at least one first line pattern (#218) extending along at least one side surface of the semiconductor chip (Figures 20-21),
the second trench structure (#T2) including at least one second line pattern (#218) extending along at least one other side surface of the semiconductor chip (Figures 20-21).
Tomura does not explicitly teach a horizontal width of the at least one first line pattern is greater than a horizontal width of the at least one second line pattern.
However, Herald teaches a comparable semiconductor package ([0033-0034]), comprising a horizontal width of at least one first line pattern is greater than a horizontal width of at least one second line pattern (Figure 7B, [0068-0069], underfill material #150 includes portions with a horizontal width #W1 greater than width #W2).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura with the teaching of Herald in order to provide additional space for injection equipment to effectively inject underfill material according to Herald, [0069].
Regarding Claim 2, Tomura in view of Herald teaches the semiconductor package as described in claim 1, wherein Tomura further teaches the underfill fills the first trench structure and the second trench structure (Figure 21 of Tomura annotated, underfill material #7 fills trenches #T1 and #T2).
Regarding Claim 5, Tomura in view of Herald teaches the semiconductor package as described in claim 1, wherein Tomura further teaches a depth of the at least one first line pattern is greater than a depth of the at least one second line pattern (Figure 21-22, [0105], depth #D11 of portion #208 is greater than depth #D12 of portion #218).
Regarding Claim 6, Tomura in view of Herald teaches the semiconductor package as described in claim 1, wherein Tomura further teaches a portion of an inner wall of the at least one first line pattern is an inclined surface (Figure 21, inner surface #218a is inclined).
Regarding Claim 7, Tomura in view of Herald teaches the semiconductor package as described in claim 1, wherein Tomura further teaches an outer wall of the at least one second line pattern is closer to the semiconductor chip than an outer wall of the at least one first line pattern (see rejection of claim 1 regarding horizontal width of first line pattern being greater than second line pattern, accordingly, outer wall of a smaller horizontal width portion #218 is closer to chip #2).
Regarding Claim 8, Tomura in view of Herald teaches the semiconductor package as described in claim 1, wherein Tomura further teaches portions of the first trench structure and portions of the second trench structure vertically overlap the semiconductor chip (Figure 20-21, #208/#218 vertically overlap chip #2).
Regarding Claim 9, Tomura in view of Herald teaches the semiconductor package as described in claim 1, wherein Tomura further teaches the first trench structure further includes a first hole pattern at an end of the first trench structure (Figure 20 of Tomura annotated, holes #H1 correspond to openings/trenches in the upper surface of the substrate, see Figures 21-22), the first hole pattern (#H1) adjacent to one of corners of the semiconductor chip (corner of chip #2).
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Tomura does not explicitly teach a horizontal width of the first hole pattern is greater than the horizontal width of the at least one first line pattern.
However, Herald teaches a horizontal width of a first hole pattern is greater than a horizontal width of at least one first line pattern (Figure 7B, [0067], an additional opening #420 has a greater width/diameter than width #W1 to provide suitable injection hole for injecting underfill material).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura with the teaching of Herald for reason set forth in rejection of claim 1.
Regarding Claim 10, Tomura in view of Herald teaches the semiconductor package as described in claim 9, wherein Tomura further teaches the substrate includes a gap region without a trench structure (Figure 20 of Tomura annotated, gap #G without recess portions #208/#218), the gap region between the first hole pattern and the at least one second line pattern (#G is between recess portions #208/#218).
Regarding Claim 11, Tomura in view of Herald teaches the semiconductor package as described in claim 9, wherein Tomura further teaches the at least one first line pattern of the first trench structure includes a plurality of first line patterns (#208/#218, Figures 20-21 of Tomura annotated), and the first trench structure further includes a second hole pattern (#H2) between the plurality of first line patterns (#208/#218), the second hole pattern (#H2) adjacent to another one of the corners of the semiconductor chip (corner of chip #2).
Tomura does not explicitly teach a horizontal width of the second hole pattern is greater than the horizontal width of the plurality of first line patterns.
However, Herald teaches a horizontal width of the second hole pattern is greater than the horizontal width of the plurality of first line patterns (Figure 7B, [0057], the additional opening #420, having a greater width/diameter than width #W1, can be positioned at different locations suitable for filling underfill material).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura with the teaching of Herald in order to provide suitable injection holes at suitable locations for injecting underfill material according to Herald, [0057], or as a mere obvious duplication of parts (MPEP §2144.04.VI.B).
Regarding Claim 12, Tomura in view of Herald teaches the semiconductor package as described in claim 11, wherein Tomura further teaches the horizontal width of the second hole pattern is greater than or equal to the horizontal width of the first hole pattern (Figure 22 or 1-3, [0069], holes corresponding to the recess/trenches in the substrate have a same width).
Regarding Claim 13, Tomura in view of Herald teaches the semiconductor package as described in claim 9, wherein Tomura further teaches the at least one second line pattern of the second trench structure includes a plurality of second line patterns (#208/#218, Figures 20-21 of Tomura annotated), and the second trench structure further includes a second hole pattern (#H3) between the plurality of second line patterns (#208/#218), the second hole pattern (#H3) adjacent to another one of the corners of the semiconductor chip (corner of chip #2).
Tomura does not explicitly teach a horizontal width of the second hole pattern is greater than the horizontal width of the plurality of second line patterns.
However, Herald teaches a horizontal width of the second hole pattern is greater than the horizontal width of the plurality of second line patterns (Figure 7B, [0057], the additional opening #420, having a greater width/diameter than width #W2, can be positioned at different locations suitable for filling underfill material).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura with the teaching of Herald in order to provide suitable injection holes at suitable locations for injecting underfill material according to Herald, [0057], or as a mere obvious duplication of parts (MPEP §2144.04.VI.B).
Regarding Claim 14, Tomura teaches a semiconductor package ([0064]), comprising:
a substrate (#4, Figure 21 of Tomura annotated) defining a first trench structure (#T1) and a second trench structure (#T2) in an upper surface of the substrate (#4);
a semiconductor chip (#2) disposed on the substrate (#4); and
an underfill (#7) filling a space between the substrate (#4) and the semiconductor chip (#2),
the first trench structure (#T1) and the second trench structure (#T2) surrounding the semiconductor chip (#2),
the first trench structure (#T1) including at least one first line pattern (#218) extending along at least one side surface of the semiconductor chip (Figures 20-21),
the second trench structure (#T2) including at least one second line pattern (#218) extending along at least one other side surface of the semiconductor chip (Figures 20-21),
the underfill (#7) including a first buried portion filling the at least one first line pattern (buried portion #BP1 in trench #T1) and a second buried portion filling the at least one second line pattern (buried portion #BP2 in trench #T2).
Tomura does not explicitly teach a horizontal width of the first buried portion is greater than a horizontal width of the second buried portion.
However, Herald teaches a comparable semiconductor package ([0033-0034]), comprising a horizontal width of the first buried portion (see above rejection regarding the buried portions of underfill material) is greater than a horizontal width of the second buried portion (Figure 7B, [0068-0069], underfill material #150 includes portions with a horizontal width #W1 greater than width #W2).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura with the teaching of Herald in order to provide additional space in the trench for injection equipment to effectively inject underfill material according to Herald, [0069].
Regarding Claim 15, Tomura in view of Herald teaches the semiconductor package as described in claim 14, wherein Tomura further teaches the underfill further includes a first protrusion and a second protrusion protruding from the first buried portion in a horizontal direction (Figures 20-21 of Tomura annotated and Figure 22, recess portions #208 include such as buried portions #BP1 protruding into the substrate), the first and second protrusions adjacent to corners of the semiconductor chip (buried portions #BP1 corresponding to holes #H1 adjacent to corners of chip #2).
Regarding Claim 16, Tomura in view of Herald teaches the semiconductor package as described in claim 15, wherein Tomura further teaches the underfill further includes a third protrusion protruding from the second buried portion in the horizontal direction (Figures 20-21 of Tomura annotated and Figure 22, recess portions #208 include buried portion such as #BP2 protruding into the substrate), the third protrusion adjacent to another one of the corners of the semiconductor chip (protruding buried portion #BP2 corresponding to hole #H2 adjacent to a corner of chip #2).
Regarding Claim 17, Tomura in view of Herald teaches the semiconductor package as described in claim 15, wherein Tomura further teaches the underfill further includes a third protrusion protruding in a direction away from the semiconductor chip (Figures 20-21 of Tomura annotated, recess portions #218 include buried portions #BP1-2 protruding away from chip #2), the third protrusion between the first protrusion and the second buried portion (Figure 20 of Tomura annotated, the protruding buried portion of recess #218 is between protruding buried portions corresponding to holes #H1 and #H2).
Regarding Claim 19, Tomura teaches a semiconductor package ([0064]), comprising:
a substrate (#4, Figure 21 of Tomura annotated) defining a first trench structure (#T1) and a second trench structure (#T2) in an upper surface of the substrate (#4);
a semiconductor structure (#2) disposed on the substrate (#4);
chip connection terminals (#6) between the substrate (#4) and the semiconductor structure (#2); and
an underfill (#7) filling a space between the substrate (#4) and the semiconductor structure (#2) and between the chip connection terminals (#6),
the first trench structure (#T1) and the second trench structure (#T2) surrounding the semiconductor structure (#2),
the first trench structure including
first line patterns (#208/#218) extending along a first side surface and a second side surface of the semiconductor structure (Figure 20, #218 extend on different surfaces of chip #2),
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first hole patterns (Figure 20 of Tomura annotated, holes #H1 correspond to openings/trenches in the substrate, see Figures 21-22) adjacent to a first corner and a third corner of the semiconductor structure (holes #H1 are adjacent to corners of chip #2), the first hole patterns (#H1) communicating with the first line patterns (#208/#218), and
a second hole pattern (#H2) communicating with the first line patterns (#208/#218), the second hole pattern (#H2) adjacent to a second corner of the semiconductor structure (corner of chip #2).
the second trench structure (#T2, Figure 21 of Tomura annotated) including second line patterns (#208/#218, Figure 20 of Tomura annotated) extending along a third side surface (#S3) and a fourth side surface (#S4) of the semiconductor structure (#2), the third side surface (#S3) opposite to the first side surface (#S1), and the fourth side surface (#S4) opposite to the second side surface (#S2).
Tomura does not explicitly teach a horizontal width of the at least one first line pattern is greater than a horizontal width of the at least one second line pattern.
However, Herald teaches a comparable semiconductor package ([0033-0034]), comprising a horizontal width of at least one first line pattern is greater than a horizontal width of at least one second line pattern (Figure 7B, [0068-0069], underfill material #150 includes portions with a horizontal width #W1 greater than width #W2).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura with the teaching of Herald in order to provide additional space in the trench for injection equipment to effectively inject underfill material according to Herald, [0069].
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Tomura in view of Herald, and further in view of US7413927A1; Patwardhan et al.; (hereinafter “Patwardhan”).
Regarding Claim 3, Tomura in view of Herald teaches the semiconductor package as described in claim 1.
Tomura in view of Herald does not explicitly teach the horizontal width of the at least one first line pattern is about 4 mm to about 5 mm.
However, Patwardhan teaches a flip chip package (col. 2, ln. 14-26), wherein a horizontal width of at least one first line pattern is about 4 mm to about 5 mm (Figures 3-4, col. 4, ln. 14, grooves #20 in a wafer containing underfill material #22 has a width of such as 4 mm).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the overlapping portion of the ranges disclosed by Patwardhan in order to increase the amount of underfill material formed in the periphery area of the chip that results in enhanced robustness according to Patwardhan, col. 2, ln. 19-26.
Regarding Claim 4, Tomura in view of Herald teaches the semiconductor package as described in claim 1, wherein Tomura further teaches the horizontal width of the at least one second line pattern is about 2 mm to about 3 mm.
Tomura in view of Herald does not explicitly teach the horizontal width of the at least one second line pattern is about 2 mm to about 3 mm.
However, Patwardhan teaches a horizontal width of at least one second line pattern is about 2 mm to about 3 mm (Figures 3-4, col. 4, ln. 14, grooves #20 in a wafer containing underfill material #22 has a width ranged 1-4 mm, or such as 2.5 mm).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the overlapping portion of the ranges disclosed by Patwardhan in order to increase the amount of underfill material formed in the periphery area of the chip that results in enhanced robustness according to Patwardhan, col. 2, ln. 19-26.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Tomura in view of Herald, and further in view of US20020127774A1; Chiu et al.; (hereinafter “Chiu”)
Regarding Claim 18, Tomura in view of Herald teaches the semiconductor package as described in claim 14.
Tomura in view of Herald does not teach a dam structure on the substrate, the dam structure surrounding the first trench structure and the second trench structure, and the underfill is in contact with a side surface of the dam structure.
However, Chiu teaches a flip-chip packaging ([0014-0015]), comprising a dam structure (#111, Figure 3D, metal dam) on the substrate (#110), the dam structure surrounding the first trench structure and the second trench structure (see rejection of claim 14 regarding trenches in the substrate, metal dam #111 surrounds underfill material #141), and the underfill (#141) is in contact with a side surface of the dam structure (#111).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura in view of Herald with the teaching of Chiu in order to provide a desire width of the underfill material for optimal resistance against thermal stress, prevent package warpage and dissipate heat from the chip according to Chiu, [0016].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tomura in view of Herald, and further in view of US20210143008A1; Ko et al.; (hereinafter “Ko”).
Regarding Claim 20, Tomura in view of Herald teaches the semiconductor package as described in claim 19.
Tomura in view of Herald does not explicitly teach the semiconductor structure includes a plurality of semiconductor elements sequentially stacked on a buffer chip.
However, Ko teaches a semiconductor package ([0005]), comprising a semiconductor structure includes a plurality of semiconductor elements sequentially stacked (#200/#210-240, Figure 1, stacked chips) on a buffer chip (#100, [0036-0037], buffer).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Tomura in view of Herald with the teaching of Ko by known methods to yield predictable results (formation of a semiconductor package comprising stacked chips on buffer/PCB substrate). See MPEP 2143(I)(A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20160099202A1 – Figures 1-5
JP2004266016A – Figures 1-4
JP2007189005A – Figures 2A-B
KR101162508B1 (IDS) – Figure 13
US20220020656A1 – Figures 2-4
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE S KIM can be reached on (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIEN TRAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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