Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 05/22/2024.
Drawing
The drawings filed on 05/22/2024 are acceptable.
Claims 1-20 are pending and have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/16/2025 is in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2021/0305809 A1), hereinafter ‘Hnng in view of Chaudhry et al. (US 9,997,509 B2), hereinafter ‘Chaudhry.
In re to claims 1, 4 and 5, Hung disclose a device (i.e. 200B, fig. 2B, see par. [0085]), comprising: a discharge device (i.e. 210, see para. [0087]) connected to a first net and a second net and (i.e. Nd1 and Nd2) configured to discharge electro-static discharge (ESD) current during an ESD event (i.e. see para. [0092]); an ESD detection circuit (i.e. pars. [0065, 0087]) connected to the discharge device (i.e. 210) and configured to detect the ESD event and activate the discharge device to discharge the ESD current during the ESD event (i.e. see para. [0092-0095]). Except, Hung fail to explicitly disclose that a latch circuit including an input and an output, the input is configured to receive a pre-charge voltage to latch the latch circuit during a pre-charge stage and track a first net voltage on the first net at the output during a ramp-up stage, the output is coupled to the discharge device to prevent activation of the discharge device during the pre-charge stage and the ramp-up stage; wherein the output of the latch circuit is connected to the RC network and the inverter input; wherein the output of the latch circuit is connected to the discharge device. Whereas, Chaudhry teach that a latch circuit (i.e. 48, fig. 2) including an input (i.e. 58) and an output (i.e. 60), the input is configured to receive a pre-charge voltage to latch (i.e. at input 58) the latch circuit during a pre-charge stage and track a first net voltage on the first net at the output during a ramp-up stage (i.e. at the output 60, see col. 5, lines 16-35) the output is coupled to the discharge device (i.e. 50) to prevent activation of the discharge device during the pre-charge stage and the ramp-up stage (i.e. see col. 4, line 63 to col. 5, line 15 and col. 5, lines 59-63); wherein the output of the latch circuit (i.e. output of 48) is connected to the RC network (i.e. 52, fig. 3) and the inverter input (i.e. inverter 92, fig. 3); wherein the output (i.e. 60, fig. 2) of the latch circuit (i.e. 48) is connected to the discharge device (i.e. 50, fig 2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Hung by incorporating the Latch of Chaudhry to detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage as taught by Chaudhry.
In re to claims 2-3, Hung disclose the device (i.e. 200B, fig. 2B, see par. [0085]) of claim 1, wherein the discharge device includes an NMOS bigfeet (i.e. see par. [0046]); wherein the ESD detection circuit includes a resistor-capacitor (RC) network (i.e. R1 and C1) and an inverter (i.e. P1 and N1, see par. [0076]) having an inverter input (i.e. Nd1/ND2) and an inverter output (i.e. ND3), the RC network is connected to the inverter input (i.e. input to circuit 202) and the discharge device is connected to the inverter output (i.e. 210 and 201 are connected by Nd1 and Nd2 power lines, see fig. 2B).
In re to claims 6-8, Hung disclose the device (i.e. 200B, fig. 2B, see par. [0085]) of claim 1. Except, Hung fail to explicitly disclose that wherein the latch circuit includes a first PMOS transistor having a first drain/source path connected to the input of the latch circuit and to a second drain/source path of a second PMOS transistor that is connected to the output of the latch circuit; wherein a first gate of the first PMOS transistor is connected to the first net; comprising a latch inverter having a latch inverter input and a latch inverter output, wherein the output of the latch circuit is connected to the latch inverter input and a second gate of the second PMOS transistor is connected to the latch inverter output; Whereas, Chaudhry teach that wherein the latch circuit (i.e. 48(2), fog. 6) includes a first PMOS transistor (i.e. 164) having a first drain/source path connected to the input of the latch circuit (i.e. 106) and to a second drain/source path of a second PMOS transistor (i.e. 162) that is connected to the output of the latch circuit (i.e. 110); wherein a first gate of the first PMOS transistor is connected to the first net (i.e. 42); comprising a latch inverter (i.e. 90 and 92, fig. 6, see col. ) having a latch inverter input (i.e. 160) and a latch inverter output (i.e. 110), wherein the output (i.e. 106) of the latch circuit 88(1), fig. 6) is connected to the latch inverter (i.e. 90(1)) input (i.e. 106) and a second gate of the second PMOS transistor (i.e. 162) is connected to the latch inverter output (i.e. 60, see fig. 6, see col. col. 10, lines 22-58). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Hung by incorporating the Latch of Chaudhry to detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage as taught by Chaudhry.
In re to claims 11, Hung disclose a device (i.e. 200B, fig. 2B, see par. [0085]), comprising: a discharge device (i.e. 210, see para. [0087]) connected to a first net and a second net and (i.e. Nd1 and Nd2) configured to discharge electro-static discharge (ESD) current during an ESD event (i.e. see para. [0092]); an ESD detection circuit (i.e. pars. [0065, 0087]) connected to the discharge device (i.e. 210) and configured to detect the ESD event and activate the discharge device to discharge the ESD current during the ESD event (i.e. see para. [0092-0095]). Except, Hung fail to explicitly disclose that a latch circuit including an input and an output, the input is configured to receive a pre-charge voltage to latch the latch circuit during a pre-charge stage and track a first net voltage on the first net at the output during a ramp-up stage, the output is coupled to the discharge device to prevent activation of the discharge device during the pre-charge stage and the ramp-up stage; wherein the latch circuit includes: a first PMOS transistor having a first gate connected to the first net and a first drain/source path connected to the input of the latch circuit; a second PMOS transistor having a second gate and having a second drain/source path connected to the first drain/source path and to the output of the latch circuit; and a latch inverter having a latch inverter input and a latch inverter output, the latch inverter input connected to the output of the latch circuit, and the latch inverter output connected to the second gate of the second PMOS transistor. Whereas Chaudhry teach that wherein the latch circuit (i.e. 90(1), fig. 6) includes a first PMOS transistor (i.e. 164) having a first gate connected to the first net (i.e. 42) and a first drain/source path (i.e. 174) connected to the input (i.e. 60) of the latch circuit (i.e. 50); a second PMOS (i.e. 162) transistor having a second gate (i.e. 66) and having a second drain/source path (i.e. 172) connected to the first drain/source path (i.e. 174) and to the output (i.e. 108) of the latch circuit output of (i.e. output of 48(1)); and a latch inverter (i.e. 90(1) having a latch inverter input (i.e. 106) and a latch inverter output (i.e. 108), the latch inverter input (i.e. 106) connected to the output of the latch circuit (i.e. (i.e. 104), and the latch inverter output (i.e. 110) connected to the second gate of the second PMOS transistor (i.e. gate of 162, see fig. 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Hung by incorporating the Latch of Chaudhry to detects an ESD event by detecting a voltage spike between a supply rail and a ground rail exceeding an ESD threshold voltage as taught by Chaudhry.
In re to claims 14-15, Hung disclose the device (i.e. 200B, fig. 2B, see par. [0085]) of claim 1, wherein the ESD detection circuit includes a resistor-capacitor (RC) network (i.e. R1 and C1) and an inverter (i.e. P1 and N1, see par. [0076]) having an inverter input (i.e. Nd1/ND2) and an inverter output (i.e. ND3), the RC network is connected to the inverter input (i.e. input to circuit 202) and the discharge device is connected to the inverter output (i.e. 210 and 201 are connected by Nd1 and Nd2 power lines, see fig. 2B). Except, Hung fail to explicitly disclose that wherein the output of the latch circuit is connected to the RC network and the inverter input; wherein the output of the latch circuit is connected to the discharge device. Whereas Chaudhry teach that wherein the output of the latch circuit (i.e. 48(2), fig. 6) is connected to the RC network (i.e. 52(1)) and the inverter input (i.e. 90(1); wherein the output (i.e. 110) of the latch circuit (i.e. 48(2)) is connected to the discharge device (i.e. 50, see fig. 6 and col. 10, lines 22-58).
In re to claims 16-19, method claims 16-19 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore, the previous rejections based on the apparatus will not be repeated.
Allowable Subject Matter
Claims 9-10, 12, 13 and 20 are objected to as being dependent upon a rejected base claims but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In re to claim 9, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “latch inverter includes a third PMOS transistor and a first NMOS transistor, the third PMOS transistor having a third drain/source path connected to the first net and to a fourth drain/source path of the first NMOS transistor that is connected to the second net”.
In re to claim 12, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “latch inverter includes a third PMOS transistor and a first NMOS transistor, the third PMOS transistor having a third drain/source path connected to the first net and to a fourth drain/source path of the first NMOS transistor that is connected to the second net”.
In re to claim 20, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein tracking the first net voltage at the output of the latch circuit during the ramp-up stage includes: receiving the inverter output at a gate of a third PMOS transistor that is connected to the first PMOS transistor and the second PMOS transistor and to the first net, wherein the first net voltage is conducted through the third PMOS transistor and the second PMOS transistor to the output of the latch circuit”.
The art of record does not disclose the above limitations, nor would it be obvious to modify the art of record to include either of the above limitations.
In re to claim 10, claim 10 depend on claim 9, thus is also objected for the same reasons provided above.
In re to claim 13, claim 13 depend on claim 12, thus is also objected for the same reasons provided above.
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838
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