DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 20200350258 A1 (hereinafter referred to as Lee), in view of Saito US 20150270304 A1 (hereinafter referred to as Saito.
Regarding claim 1, Lee teaches
A semiconductor device, comprising a cell structure ("The second structure STb' may include the memory cell array CAR, a third insulating structure IS3', the bit lines BL, connection structures 727, 729, 735, 737, and 741, supports 723, the source contact structure SCT, and second conductive contact patterns 743" para. 00132, FIG. 11) stacked on a peripheral circuit structure ("a first structure Sta”, a peripheral circuit, para. 0127, FIG. 11),
wherein the cell structure includes:
a plurality of gate electrode layers stacked on a first substrate ("The gate stacked structure
GST may include interlayer insulating layers 511 and the conductive patterns 513 stacked
alternately with each other over the second substrate 501", para. 0083, FIGs 7A and 7C. As
stated in para. 0135, "The gate stacked structure GST and the supports 723 may have the
same structures as the gate stacked structure GST and the supports 523 described above
with reference to FIG. 7A.". This stack is over “second substrate 701”, para. 0126);
a plurality of channel regions vertically penetrating the gate electrode layers ("gate stacked
structure GST may be penetrated by channel structures CH", para. 0083, FIG. 7C);
a first interlayer dielectric layer on the first substrate and covering the gate electrode layers and the channel regions ("upper insulating layer 745", para. 0138, FIG. 11);
a plurality of first metal pads exposed at the first interlayer dielectric layer and connected to the channel regions (a first plurality of "second conductive contact patterns 743” over the “memory cell array CAR” are embedded in an upper insulating layer 745” and are in contact the “pad contact plugs 741”, which contact “connection structures 729”, para. 0138, FIG 11); and
a plurality of second metal pads exposed at the first interlayer dielectric layer and connected to the gate electrode layers ("second conductive contact patterns 743” over the staircase region, to the left of “source contact structure SCT”, para. 0079, are in contact with “conductive pads 735”, para. 0137),
wherein the peripheral circuit structure includes:
at least one transistor on a second substrate ("As described above with reference to FIGS. 7A and 7B, the first structure STa' may include a peripheral circuit including the transistors TR", para 0127, on “substrate 601”, para. 0126);
a second interlayer dielectric layer on the second substrate and covering the transistor ("second insulating structure IS2'", para. 127, FIG. 11); and
a plurality of third metal pads (a first plurality of "first conductive contact patterns 633" over “memory cell array CAR”, para. 0127, FIG. 11) and a plurality of fourth metal pads ("first conductive contact patterns 633" over staircase region) exposed at the second interlayer dielectric layer and connected to the transistor,
wherein the plurality of first metal pads and the plurality of third metal pads are coupled to each other ("first conductive contact patterns 633" and “second conductive patterns 743” over “memory core region CAR” are coupled, para. 0139),
wherein the plurality of second metal pads and the plurality of fourth metal pads are coupled to each other ("first conductive contact patterns 633" and “second conductive patterns 743” over staircase region are coupled), and each of the plurality of fourth metal pads are in contact with one of the plurality of second metal pads respectively. ("first conductive contact patterns 633" and “second conductive patterns 743” over staircase region are shown as connected one to one)
However, Lee fails to teach each of the plurality of third metal pads are in contact with at least of two of the plurality of first metal pads.
Nevertheless, Saito teaches two “electrodes 2A” bonded to an individual “electrode 2B” (para. 0127 FIG. 19). There is no limit to the number of “electrodes 2A” that can be bonded so long as the area of “electrode 2B” is larger than the area of “electrodes 2A” (para. 0056 and 0127). The difference in area helps ensure contact between “electrodes 2A and 2B” even after some misalignment (para. 0056). The two or more “electrode 2A” are connected to the same “base electrode 4c”, the uppermost “wiring 4a” (para. 0075). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a plurality of smaller “second conductive patterns 743” can connect to a single “first conductive contact patterns 633”. It is obvious to try with any number of electrodes as long as the area of the corresponding “first conductive contact patterns 633” is larger.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and third metal pads in Lee with the teachings of Saito. It would have been obvious to try multiple first electrodes connected to a single third metal pad because any number of third electrodes can be made to fit within the surface area of the first metal pad. This compensates for any small misalignment.
Regarding claim 2, Lee, modified by Saito, teach the semiconductor device as claimed in claim 1, wherein a width of the plurality of third metal pads is larger than a width of the plurality of first metal pads (as combined, “first conductive contact patterns 633” are larger than the two “second conductive patterns 743” similar to how the “electrode 2A” in Saito are smaller than “electrode 2B”).
Regarding claim 3, Lee, modified by Saito, teach the semiconductor device as claimed in claim 2, wherein, at an interface between the first interlayer dielectric layer and the second interlayer dielectric layer, an area of the plurality of third metal pads is greater than an area of the plurality of first metal pads such that, when viewed in a plan view, the plurality of first metal pads are within one of the plurality of third metal pads that corresponds to the plurality of first metal pads (as combined, “first conductive contact patterns 633” have a larger area than the two “second conductive patterns 743”, similar to how the “electrode 2B” in Saito has a larger bottom area than each “electrode 2A”).
Regarding claim 9, Lee, modified by Saito, teach the semiconductor device as claimed in claim 1, wherein the plurality of second metal pads and the plurality of fourth metal pads are vertically aligned with each other ("first conductive contact patterns 633" and “second conductive patterns 743” over staircase region overlap).
Regarding claim 10, Lee, modified by Saito, teach the semiconductor device as claimed in claim 1, wherein, at an interface between the first interlayer dielectric layer and the second interlayer dielectric layer: the plurality of first metal pads and the plurality of third metal pads constitute a single body formed of the same material, and the plurality of second metal pads and the plurality of fourth metal pads constitute a single body formed of the same material (Since “first conductive contact patterns 633 and the second conductive contact patterns 743” are made of copper, para. 0139, and are bonded using heat, para. 0162, the examiner understands they form a conductive body of copper).
Regarding claim 11, Lee, modified by Saito, teach the semiconductor device as claimed in claim 1, wherein the cell structure further includes a memory cell array ("the memory cell array CAR", para. 0132),
the memory cell array including:
a plurality of cell strings ("memory strings STR", para. 0133) including a plurality of memory cells ("The source select transistor, the memory cells, and the drain select transistor may be coupled in series and may form the memory string STR", para 0087. Also, "The memory strings STR may have the same structure as the memory string STR illustrated in FIG. 7C.", para 0133);
a plurality of word lines connected to the plurality of memory cells ("conductive patterns 513", para 0087, FIG. 7A);
a plurality of bit lines connected to one side of the plurality of cell strings ("bit lines BL", para. 0132, FIG. 11); and
a ground selection line connected to the plurality of cell strings ("source region 703", para. 0133).
Allowable Subject Matter
Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art Saito teaches a lower wafer comprising groups of two first metal pads and an upper wafer comprising third metal pads. In other words, each wafer comprises the same type of pads and there is no suggestion of having large third pads and smaller first pad pairs in a same wafer. Saito fails to teach or render obvious wherein the plurality of fifth metal pads and the plurality of sixth metal pads are coupled to each other, and wherein each of the plurality of fifth metal pads are in contact with at least of two of the plurality of sixth metal pads. Therefore, claim 4 is considered to contain allowable subject matter.
Claims 5-8 are objected to based on their dependency on claim 4.
Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 12, the prior art Saito teaches a lower wafer comprising groups of two first metal pads and an upper wafer comprising third metal pads. In other words, each wafer comprises the same type of pads. There is no suggestion of having smaller sub-pads and a larger sub-pad in a same wafer. Saito fails to teach or render obvious wherein the plurality of first metal pads include a plurality of first sub-pads and a second sub-pad, wherein the plurality of third metal pads include a third sub-pad and a plurality of fourth sub-pads, wherein the plurality of first sub-pads are coupled to the third sub-pad, and a width of the third sub-pad is greater than a width of the plurality of first sub-pads, wherein the plurality of fourth sub-pads are coupled to the second sub-pad, and a width of the second sub-pad is greater than a width of the plurality of fourth sub-pads. Therefore, claim 12 is allowable.
Claims 13-20 are allowed based on their dependency on claim 12.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898