DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23, 25, 26, 31-33, 35, and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lyra et al. (U.S. Patent Application Publication Number 2011/0072284).
Regarding Claims 21 and 31, Lyra discloses a device (Figure 2, item 200) comprising:
an interface (Figure 2, item 220) connected to a bidirectional signal line (Figure 2, item 230) configured to send and receive data to and from a host computer (Figure 2, item 210, paragraph 0021); and
control circuitry configured to:
receive an instruction from the host computer to operate in a power efficient mode (Figure 2, item 250, paragraph 0012; i.e., the message requesting the USB device 200 to stop sending data on the bus 230 being equivalent to the claimed instruction to operate in a power efficient mode);
operate the device in the power efficient mode responsive to the received instruction (paragraph 0013), including to:
transition operation of the bidirectional signal line to an idle mode (paragraph 0014; i.e., by stopping the USB device 200 from transmitting data onto the bus 230, it causes the bus 230 to enter into an “idle mode” whereas when the USB device 200 begins sending data onto the bus 230, it causes the bus 230 to enter into a “transmission mode”);
operate the bidirectional signal line in the idle mode wherein data to be sent over the bidirectional signal line is stored in one or more buffers (Figure 2, item 260) of the device (paragraph 0014);
transition operation of the bidirectional signal line from the idle mode to a transmission mode (paragraphs 0015, 0038, and 0040-0041; i.e., the USB device 200 can wake up the USB host 210 and start sending data that was stored in the buffer 260 onto the bus 230 [transitioning the bus from the idle mode to the transmission mode]);
operate the bidirectional signal line in the transmission mode wherein the data stored in the one or more buffers is sent over the bidirectional signal line (paragraphs 0014 and 0038; i.e., when the buffer 260 reaches a watermark level, it can cause the USB host 210 to wake up and subsequently transmit the buffered data onto the bus 230); and
transition operation of the bidirectional signal line back to the idle mode from the transmission mode without receiving another instruction from the host computer to operate in the power efficient mode (paragraphs 0025 and 0030; i.e., the USB component 320 [located within USB device 200 - see paragraph 0026] can again request the USB host 210 to stop sending data on the bus 230, which causes the bus 230 to back to the idle mode from the transmission mode; the USB host 210 at most will acknowledge the request [paragraph 0035] but does not send “another instruction … to operate in the power efficient mode”).
Regarding Claims 22 and 32, Lyra discloses wherein the device is a peripheral device attached to the host computer (paragraph 0021; e.g., a printer or scanner).
Regarding Claims 23 and 33, Lyra discloses wherein the interface is a Universal Serial Bus (USB) serial interface (paragraph 0008).
Regarding Claims 25 and 35, Lyra discloses wherein the control circuitry is configured to transition the bidirectional line out of the idle mode when: an idle time interval has elapsed, or an amount of data stored in the one or more buffers exceeds a threshold (paragraph 0038).
Regarding Claims 26 and 36, Lyra discloses wherein the control circuitry is configured to transition the bidirectional signal line out of the transmission mode when: a transmission time interval has elapsed (paragraph 0023; i.e., the bus 230 transitions out of the transmission mode when there is no bus traffic for a specified period), or an amount of data transmitted during the transmission mode exceeds a threshold.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Lyra as applied Claims 23 and 33, and further in view of Sakaki et al. (U.S. Patent Application Publication Number 2006/0277339).
Regarding Claims 24 and 34, Lyra does not expressly disclose wherein the control circuitry is configured to use one of two data lines of the USB serial interface to send and receive data while another one of the two data lines is deactivated.
In the same field of endeavor (e.g., USB communications), Sakaki teaches wherein the control circuitry is configured to use one of two data lines (Figure 1, item 120 and 121) of the USB serial interface to send and receive data while another one of the two data lines is deactivated (paragraphs 0046 and 0065; i.e., single ended data transmission can occur, in which only the D+ line of the USB bus is used, while the D- line is not used [deactivated]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Sakaki’s teachings of USB communications with the teachings of Lyra, for the purpose of reducing the amount of power required to transmit data over the USB bus.
Claims 27, 28, 37, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Lyra as applied Claims 21 and 31, and further in view of Cohen (U.S. Patent Application Publication Number 2006/0050777).
Regarding Claims 27 and 37, Lyra does not expressly disclose wherein the control circuitry is configured to encode a multi-bit symbol as a series of pulses to transmit the multi-bit symbol over the bidirectional signal line.
In the same field of endeavor (e.g., bus communications), Cohen teaches wherein the control circuitry is configured to encode a multi-bit symbol as a series of pulses to transmit the multi-bit symbol over the bidirectional signal line (Figure 2B, paragraphs 0005, 0016, and 0023; i.e., a multi-bit symbol could be 0100 as shown in Figure 2B, which would result in a high pulse of a particular duration followed by a low pulse of a particular duration).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Cohen’s teachings of bus communications with the teachings of Lyra, for the purpose of being able to support a wider variety of symbols on the bus. More specifically, by encoding different symbols as different series of pulses, the system would be able to accommodate more symbols.
Regarding Claims 28 and 38, Cohen teaches wherein the control circuitry is configured to encode different multi-bit symbols as different numbers of pulses (Figure 2B, paragraphs 0005, 0016, and 0023; i.e., one symbol could be 0100, which uses two pulses, while another symbol could be 110000, which uses three pulses).
Claims 29 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Lyra as applied Claims 21 and 31, and further in view Mishra et al. (U.S. Patent Application Publication Number 2014/0108679).
Regarding Claims 29 and 39, Lyra discloses wherein the control circuitry is configured to receive a series of pulses over the bidirectional signal line; decode the series of pulses received to determine a multi-bit symbol (paragraph 0023; i.e., Lyra discloses the use of the USB 2.0 Standard; as is known in the art and evidenced by the attached USB 2.0 Standard, USB control circuitry decodes series of pulses [Section 7.1.8] received to determine multi-bit symbols [e.g., Section 7.1.7.4.2]).
Lyra does not expressly disclose using the multi-bit symbol to map a previous pin state of the interface to a current pin state of the interface.
In the same field of endeavor (e.g., symbol communication techniques), Mishra teaches using the multi-bit symbol to map a previous pin state of the interface to a current pin state of the interface (paragraphs 0032, 0036, and claim 12; i.e., the finite state machine identifies the changes to the virtual GPIO pins based on a mapping of the virtual GPIO signals [the claimed “multi-bit symbol” - see paragraph 0034]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Mishra’s teachings of symbol communication techniques with the teachings of Lyra, for the purpose of being able to more quickly identify if there are changes in the received pulses, thereby saving the receiver time (it would not need to read the incoming signals again if the state of the pins has not changed).
Claims 30 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Lyra as applied Claims 23 and 33, and further in view of what was well known in the art.
Regarding Claims 30 and 40, Lyra does not expressly disclose wherein the device is configured to transfer a 2-bit state to the host computer over the bidirectional signal line in a 90-nanosecond time interval. However, Lyra uses the USB standard (paragraph 0023), which allows for various bit time intervals based on the selected operating speed (e.g., low speed, full speed, or high speed). It would have been obvious to one of ordinary skill in the art to transfer a 2-bit state in a 90-nanosecond time interval as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Transmitting a number of bits in a smaller time interval would allow for more data to be transmitted each second.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a method for buffering data to be transmitted onto a bus during an idle mode.
Response to Arguments
Applicant's arguments filed 4/2/26 have been fully considered but they are not persuasive.
Regarding Claim 21, Applicant argues “[a]s discussed above in the interview summary, the Examiner agreed that this recited transition, performed without receiving another instruction from the host computer to operate in the power efficient mode, would overcome the rejection.” Response, page 9. However, as discussed in the § 102 rejection, Lyra discloses the argued feature. More specifically, Lyra discloses that the USB component 320 (located within USB device 200 - see paragraph 0026) can again request the USB host 210 to stop sending data on the bus 230, which causes the bus 230 to back to the idle mode from the transmission mode. See Lyra, paragraphs 0025 and 0030. The USB host 210 at most will acknowledge the request (paragraph 0035) but does not send “another instruction … to operate in the power efficient mode”. Accordingly, it can be seen that Lyra does in fact disclose the argued limitation.
Therefore, the claims stand as previously rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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