DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Objections
2. Claims 1 & 9 are objected to because of the following informalities:
In claims 1 & 9, lines 2-4, the word “memory (IC) dies” should be changed to “memory IC dies” to be consistent with other dependent claims that recite the similar words “memory IC dies”, see claims 2-8 and 10-14 as example.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-4, 6-13 and 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yudanove et al (US 11,604,754).
The applied reference has a common assignee (AMD, Inc.) with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regrading the independent claims 1, 9 & 18, Yudanove (see Figs. 2 to 5) clearly shows an integrated circuit (IC) memory device, comprising: at least two or more memory (IC) stacking dies (222, see Fig. 2) forming a memory die stack; and at least two non-memory IC dies (221) containing a “controller circuitry” acting as an “in-die logic circuitry”, interposed between adjacent memory die stacks (222), and Fig. 4 also shows usage of vertical wirings or vertical TSVs (i.e., formed as conductive vias or through-holes) so that each logic/control die 221 also having an output routed to circuitry of the memory IC dies 222 through these TSVs passing through the memory die stack, and Fig. 3B further shows that the in-die logic circuitry (from each logic die 221) comprising at least one control circuitry (225) for performing at least the logic functions of row segmentation logic, and/or other conventional logic circuitry for many memory devices such as, for example, a plurality of sense amplifiers, a or row/column select logic circuitry. Particular, see Figs. 3A-3C showing each the stacked memory dies 220 can be divided into plurality of row segments (M0 & M1), with M1 for the first row and M0 for the second row as an example. Thus, based on these divided segments, the logic die can address each row based on different assigned segment addresses from each die/chip accordingly.
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Memory dies 220, and many
many mats (M0 or M1) per row)]
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[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Vertical TSVs)][AltContent: arrow][AltContent: textbox (Logic dies 221 with TSV for
I/O communications)]
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Additionally, Fig. 5 shows address matrix (X-bar) for addressing each individual memory die such as transmitting address from its row decoder (inside the logic die) to each memory die and select data from a particular segment (M0 or M1) or a data potion each row data under a same word line address if desired.
Claim 2 & 10-11, Fig. 2 shoes each logic die (or non-memory IC die) is disposed between two adjacent memory dies of the die stack, and the bottom logic die 222 in Fig. 4, which is also adjacent the top memory die stack, could be formed on top surface of a bottom substrate as conventional support as well.
Claim 3, both Figs. 2 & 4 shows the bottom logic die (222) contacts only one memory die, which is located right above it, by usage of vertical TSVs.
Claims 4 & 12, Fig. 5 shows usage of an address buffer (X-bar 226) inside a middle/buffer die (221) for buffering the addressing signals from each word line drivers, if any, of each memory die 222 to their respective coupling logic die (221), see col. 6.
Claim 6-7, 13 & 15-20, col. 7 (lines 46-56) mentions each logic/non-memory die includes other necessary circuitry for controlling operations of each memory die such as, i.e., row/column select circuitry, row segmentation circuitry (see Fig. 3, M0 or M1), and sense amplifiers (SAs), etc., for the purpose of sensing data bits, reading bits or writing bits from each memory die through the control/logic die if desired by user.
Claim 8, Fig, 3A-3C above shows if each segment (M0 or M1) could be formed as a conventional “memory mat”, then at least one or more than two of such mats per row could be selected using a common word line address as well. For example, Fig. 3A-3C shows at least three different mats (M1) are sharing a same row address and same WL select logic signals.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 5 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over teachings of Yudanove et al (US 11,604,754) cited above in further view of Yu et al (US 11,171,076).
Claims 5 & 14, depending on rejected claim 1 & 9 above, and further add the limitations of using “hybrid bonding” technique in forming signal routing circuity between adjacent memory dies as well as adjacent logic dies through the vertical TSVs, which is not clearly suggested by Yudanove reference; however, such knowledge is considered as conventional techniques in other prior art teachings.
For example, Yu et al (Fig. 1) shows a stacked dies including a plurality of memory dies (M1 to M3) stacked upon each other, together with a plurality of other/logic dies (L1 to L4) also staked upon each other, forming a whole integrated circuit package. Particularly, para [0030] stated that bonding between various logic dies and memory dies are of “hybrid bonding” type; thus, would have obviously suggest to a skilled person in this art to form similar hybrid bonding in Yudanove’s device as both teachings are also related to a similar concept of bonding two different types of dies (logic and memory) together. Additionally, any skilled person would have motivated to use this hybrid bonding technique for ease of manufacturing for the purpose of reducing its total costs or complexity as well. See [0030] below:
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5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827