DETAILED ACTION
This action is responsive to the following communications: the Application filed May 22, 2024, and Response to Election / Restriction filed December 01, 2025.
Claims 1-21 are pending. Claims 4-21 are withdrawn from consideration as being drawn to non-elected inventions. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 22, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Species 2 in the reply filed on 12/01/2025 is acknowledged. The applicant argues in the reply that Species 1 and Species 2 are nearly identical, and therefore should be combined into a single Species for examination. The applicant’s argument is persuasive. Whether shorted or not, the cells are identical and functionally equivalent. Accordingly, the examiner combines Species 1 and Species 2 and examines the claims under Species 1 and Species 2.
The applicant classifies claims 1-3, 8-11, 13 and 18-21 into Species 1 and Species 2.
However, claims 8, 10-11, 13 and 18-21, as elected by the applicant, are dependent on the unelected claims. In other words, for example, the limitations of claim 8 include both the limitations of claim 5 that are not elected and the limitations of claim 8 itself.
Accordingly, the examiner examines the claims corresponding to the Species 1 and Species 2 elected by the applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 7,606,062) in view of Sinangil et al. (US 2024/0055048).
Regarding independent claim 1, Hsu et al. teach a multi-port-cell memory comprising:
an array of memory cells (FIG. 2), each memory cell (FIG. 1) comprising:
a first pull-up p-channel transistor (102) having a source connected to a power supply (Vcc symbol), a drain connected to a first node (112), and a gate connected to a second node (110);
a first pull-down n-channel transistor (104) having a source connected to a ground voltage supply (GND symbol), a drain connected to the first node (112), and a gate connected to the second node (110);
a second pull-up p-channel transistor (106) having a source connected to the power supply (Vcc), a drain connected to the second node (110), and a gate connected to the first node (112);
a second pull-down n-channel transistor (108) having a source connected to the ground voltage supply (GND), a drain connected to the second node (110), and a gate connected to the first node (112);
a first n-channel pass transistor (114) having a gate connected to a write word line (118), and a channel connected between the first node (112) and a first write bit line (122);
a second n-channel pass transistor (116) having a gate connected to the write word line (118), and a channel connected between the second node (110) and a second write bit line (120);
a first p-channel pass transistor (128) having a gate connected to an inverse write word line (132), and a channel connected between the first node (112) and the first write bit line (122);
a second p-channel pass transistor (130) having a gate connected to the inverse write word line (132), and a channel connected between the second node (110) and the second write bit line (120);
a read-port inverting p-channel transistor having a gate connected to the second node, a source connected to the power supply, and a drain connected to a first read-port node;
a read-port pass p-channel transistor having a gate connected to an inverse read word line, and a channel connected between the first read-port node and a read bit line;
a read-port inverting n-channel transistor (124) having a gate connected to the second node (110), a source connected to the ground voltage supply (GND symbol), and a drain connected to a second read-port node (the node between 124 and 126); and
a read-port pass n-channel transistor (126) having a gate connected to a read word line (134), and a channel connected between the second read-port node (the node between 124 and 126) and the read bit line (138);
wherein each row in the array of memory cells has a write word line (118), an inverse write word line (132), a read word line (134), and an inverse read word line that connect to memory cells in a row (see FIGS. 1-2);
wherein each column in the array of memory cells has a first write bit line (122), a second write bit line (120), and a read bit line (136) that connect to memory cells in the column (FIGS. 1-2),
whereby the memory cell has four word lines and three bit lines (120, 122 and 136).
Hsu et al. are silent with respect to a read port of SRAM memory cell.
Sinangil et al. teach the deficiencies in e.g., FIG. 1 and accompanying disclosure, i.e., a read-port inverting p-channel transistor (M9) having a gate connected to the second node (116, i.e., Hsu’s the second storage node 110), a source connected to the power supply (104), and a drain connected to a first read-port node (the node between M9 and M10);
a read-port pass p-channel transistor (M10) having a gate connected to an inverse read word line (RWLB), and a channel connected between the first read-port node (the node between M9 and M10) and a read bit line (RBL); and
wherein each row in the array of memory cells has a write word line (WL), an inverse write word line (WLB), a read word line (RWL), and an inverse read word line (RWLB) that connect to memory cells in a row (see FIGS. 1, 3 and 5).
whereby the memory cell has four word lines (WL, WLB, RWL and RWLB).
Hsu and Sinangil are analogous art because they both are directed to SRAM memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu with the specified features of Sinangil because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Sinangil et al. to the teaching of Hsu et al. such that a memory, as taught by Hsu et al., utilizes a read port, as taught by Sinangil et al., for the purpose of operating low voltage of read operations (see Sinangil’s paragraph [0032]), thereby enhancing read/write memory operations.
Regarding claim 2, Hsu et al. and Sinangil et al., as combined, teach the limitations of claim 1.
Hsu et al. further teach the power supply is a logic power supply that is also used by logic cells in a chip that includes the multi-port- cell memory;
wherein each row further comprises:
a write word line driver (FIG. 2 along with FIG. 1: wrwl) that drives the power supply onto the write word line when the row is selected and being written, and that connects the ground voltage supply to the write word line when the row is not selected and being written;
an inverse write word line driver (FIG. 2 along with FIG. 1: wrwl#) that connects the ground voltage supply to the inverse write word line when the row is selected and being written, and that connects the power supply voltage to the inverse write word line when the row is not selected and being written;
a read word line driver (FIG. 2 along with FIG. 1: rdwl) that drives the power supply onto the read word line when the row is selected and being read, and that connects the ground voltage supply to the read word line when the row is not selected and being read;
wherein each column further comprises:
a write bit line driver (FIG. 2 along with FIG. 1: wrbl) that connects the power supply to the first write bit line when an input data bit is high and writing is enabled, and that connects the ground voltage supply to the first write bit line when the input data bit is low and writing is enabled;
an inverse write bit line driver (FIG. 2 along with FIG. 1: wrwl#) that connects the power supply to the second write bit line when the input data bit is low and writing is enabled, and that connects the ground voltage supply to the second write bit line when the input data bit is high and writing is enabled;
Sinangil et al. further teach an inverse read word line driver (FIG. 5 along with FIG. 1: RWLB) that connects the ground voltage supply to the inverse read word line when the row is selected and being read, and that connects the power supply voltage to the inverse read word line when the row is not selected and being read;
a read amplifier (FIG. 3: 310 or FIG. 5: 516) that generates an output data bit that is high when the read bit line is high during a read, and that generates the output data bit that is low when the read bit line is low during a read; wherein the first write bit line and the second write bit line are not connected to the read amplifier and are not used for reading but only for writing.
Further, a sense amplifier utilizes read bit lines, without connecting write bit lines in a memory device for performing memory read operations is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a sense amplifier for performing date read operations because these conventional technology are well established in the art of the memory devices.
Regarding claim 3, Hsu et al. and Sinangil et al., as combined, teach the limitations of claim 2.
Siangil et al. further teach a metal line that shorts together the first read-port node (M10 source node) and the second read-port node (M11 source node) (i.e., whether shorted or not, the cells are identical and functionally equivalent, as the applicant acknowledged); wherein the read-port pass p-channel transistor and the read-port pass n-channel transistor comprise a transmission gate (FIG. 1: 130).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Siangil et al. for the same purpose of operating low voltage of read operations, thereby enhancing read/write memory operations.
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825