DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-8 are presented for examination.
Priority
The instant application has been identified by applicant as a divisional of parent application 17/678,040. However, due to the inclusion of claims 1-5 in the instant application, the instant application is a continuation of parent application 17/678,040 as the subject matter of instant claims 1-5 is covered by the elected group of the aforementioned parent application.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/678,040, filed on 2/23/2022.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12/034,002 (hereinafter US Patent). Although the claims at issue are not identical, they are not patentably distinct from each other because
As to claim 1: Claim 2, which incorporates all limitations of independent claim 1, of US Patent teaches all limitations of instant claim 1 where the first surface is interpreted to be above the second surface and is the surface on which the first metal layer is formed.
As to claim 2: Claim 3, which incorporates all limitations of independent claim 1 and dependent claim 2, of US Patent teaches all limitations of instant claim 2.
As to claim 3: Claim 2 of US Patent inherently teaches instant claim 3 as the transistor circuit will be formed on one of the major surfaces of the substrate (the first or second surface).
As to claim 4: Claim 1 of US Patent teaches all limitations of instant claim 4.
Claim Objections
Claim 8 is objected to because of the following informalities: in line 5, "the transistor" should be amended to read -a transistor-. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hohlfeld et al (US 2015/0130071 and Hohlfeld hereinafter).
As to claims 6-8: Hohlfeld discloses [claim 6] a manufacturing method of an electronic apparatus (Figs. 1-3; 100; [0015]), comprising: providing a carrier substrate (Fig. 1; 10 is interpreted to be a carrier substrate as other features of the apparatus 100 are formed thereon; [0015]); forming a first metal layer (Fig. 1; 16A; [0019]) having an opening (gap between adjacent 16A) on the carrier substrate (10); forming a first insulating layer (portion of 22 between 16A and 23; [0024] and [0030]) on the first metal layer (16A), and a first surface (bottom surface of 22 that contacts the top surface of 16A) of the first insulating layer (portion of 22 between 16A and 23) contacts the first metal layer (16A); and forming a second metal layer (23 will inherently have metal therein to form connections to 21 and 24; 23 as a whole is interpreted to be the second metal layer as it is metal containing; [0030]-[0031]) on the first insulating layer (portion of 22 between 16A and 23), and a second surface (top surface of 22 between 16A and 23 that directly touches the bottom surface of 23) of the first insulating layer (between 16A and 23) contacts the second metal layer (bottom surface of 23), wherein the first surface (bottom surface) is opposite to the second surface (top surface), and a projection of the opening (gap between adjacent 16A) on the second surface (top surface of 22 between 16A and 23 that directly touches the bottom surface of 23) is overlapped with a projection of the second metal layer (23) on the second surface (top surface of 22 between 16A and 23 that directly touches the bottom surface of 23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hohlfeld in view of Tamaki et al (US 2013/0314834 and Tamaki hereinafter).
Hohlfeld discloses further comprising: forming a circuit (Fig. 1; 21 is a circuit that drives transistors; [0016]) on the first insulating layer (portion of 22 between 16A and 23); forming a routing layer (Figs. 1 and 3; routing layer is 26 within 22; 26 is interpreted to be a routing layer as it routes a signal to the modules 10 and 20; [0033]) on (26 is on/over the top and sidewalls of parts of the first insulating layer) the first insulating layer (portion of 22 between 16A and 23), and electrically connecting the routing layer (26 within 22) with the circuit (circuit 21 is connected to 26 through 23 and 23.2; [0033]); forming a second insulating layer (portion of 22 over the top surface of 21 and 23; [0033]) covering the second metal layer (23), the circuit (21), and the routing layer (portion of 26 within 22 between 16A and 23) on the first insulating layer (portion of 22 between 16A and 23); disposing an electronic assembly (26 outside of 22 is interpreted to be an electronic assembly as it is a part of an electronic device; claim doesn’t indicate what comprises an electronic assembly) on (26 outside of 22 is on/over 22) the second insulating layer (portion of 22 over the top surface of 21 and 23), and electrically connecting (through 23 and 23.2; [0033]) the electronic assembly (26 outside of 22 is interpreted to be an electronic assembly) with the circuit (21), the first metal layer (16A through 11 and 12A), and the second metal layer (23); and electrically connecting a control circuit (device from which control signal in Figs. 3A and 3B is provided is interpreted to be a control circuit as control signals are provided and it will inherently be a circuit; [0035]) with the routing layer (26 within 22).
Hohlfeld fails to expressly disclose where [claim 7] the circuit is a transistor circuit.
Hohlfeld discloses that the circuit is a driver circuit, see [0030].
Tamaki discloses in Fig. 1 a driving circuit 300 that comprises transistors 1a and 1b, see [0019], and is thus interpreted to be a transistor circuit.
Given the teachings of Tamaki, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Hohlfeld by employing the well-known or conventional features of driver circuit fabrication, such as displayed by Tamaki, by employing transistors in the driver circuit in order to low power consumption driving circuit that allows for reduced power consumption ([0010]).
Allowable Subject Matter
Claims 5 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: as to claim 8, the closest prior art Hohlfeld discloses further comprising: forming a routing layer (Figs. 1 and 3; routing layer is 26 within 22; 26 is interpreted to be a routing layer as it routes a signal to the modules 10 and 20; [0033]) on (26 is on/over the top and sidewalls of parts of the first insulating layer) the first insulating layer (portion of 22 between 16A and 23); forming a second insulating layer (portion of 22 over the top surface of 21 and 23; [0033]) covering the second metal layer (23) and the routing layer (routing layer is 26 within 22) on the first insulating layer (portion of 22 between 16A and 23); electrically connecting (through 23 and 23.2) the transistor circuit (21) with the routing layer (26 within 22); disposing an electronic assembly (26 outside of 22 is interpreted to be an electronic assembly as it is a part of an electronic device; claim doesn’t indicate what comprises an electronic assembly) on the second insulating layer (portion of 22 over the top surface of 21 and 23), and electrically connecting the electronic assembly (26 outside of 22) with the transistor circuit (21), the first metal layer (26 through 12A and 11), and the second metal layer (23); and electrically connecting a control circuit (device from which control signal in Figs. 3A and 3B is provided is interpreted to be a control circuit as control signals are provided and it will inherently be a circuit; [0035]) with the routing layer (26 within 22). Hohlfeld fails to expressly disclose disposing the transistor circuit on the second insulating layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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